参数资料
| 型号： | X5163P-2.7A |
| 厂商： | Intersil |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 16K EE 8-DIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.92V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
X5163, X5165
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL = 1, the latch is set
STATUS REGISTER BITS
WATCHDOG TIME OUT
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
WD1
1
1
WD0
0
1
(TYPICAL)
200 milliseconds
disabled
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon power-
up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.
STATUS
REGISTER BITS
ARRAY ADDRESSES PROTECTED
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
BL1
0
0
1
1
BL0
0
1
0
1
X516X
None
$0600-$07FF
$0400-$07FF
$0000-$07FF
provide an In-Circuit Programmable ROM function (Table
2). WP is LOW and WPEN bit programmed HIGH disables
all Status Register Write Operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog bits
from inadvertent corruption.
In the locked state (Programmable ROM Mode) the WP pin
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s Status Register.
Setting the WP pin LOW while WPEN is a “1” while an
STATUS REGISTER BITS
WATCHDOG TIME OUT
internal write cycle to the Status Register is in progress will
not stop this write operation, but the operation disables
WD1
0
0
WD0
0
1
(TYPICAL)
1.4 seconds
600 milliseconds
subsequent write attempts to the Status Register.
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
SCK
INSTRUCTION
16 BIT ADDRESS
SI
15
14
13
3
2
1
0
DATA OUT
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
8
FN8128.3
June 1, 2006
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