参数资料
| 型号： | X5163PI-2.7A |
| 厂商： | Intersil |
| 文件页数： | 9/21页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 16K EE 8-DIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.92V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
X5163, X5165
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting the
WPEN bit in the Status Register to “0” blocks the WP pin
function, allowing writes to the Status Register when WP is
HIGH or LOW. Setting the WPEN bit to “1” while the WP pin
is LOW activates the Programmable ROM mode, thus
requiring a change in the WP pin prior to subsequent Status
Register changes. This allows manufacturing to install the
device in a system with WP pin grounded and still be able
to program the Status Register. Manufacturing can then
load Configuration data, manufacturing time and other
parameters into the EEPROM, then set the portion of
memory to be protected by setting the block lock bits, and
finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The address
is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address is
reached, the address counter rolls over to address $0000
allowing the read cycle to be continued indefinitely. The read
operation is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 5).
To read the Status Register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the Status Register
are shifted out on the SO line. Refer to the Read Status
Register Sequence (Figure 6).
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Operation will be
ignored.
9
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 8).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 0 and
1 must be “0”.
While the write is in progress following a Status Register or
EEPROM Sequence, the Status Register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
? The device is in the low power standby state.
? A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
? SO pin is high impedance.
? The Write Enable Latch is reset.
? The Flag Bit is reset.
? Reset Signal is active for t PURST .
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
? A WREN instruction must be issued to set the Write Enable
Latch.
? CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
FN8128.3
June 1, 2006
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| X5163PIZ-2.7 | 功能描述:IC CPU SUPERV 16K EEPROM 8-PDIP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 600 ms 电压 - 阀值:3.8V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) |
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