参数资料
| 型号： | X5323PI-2.7 |
| 厂商： | Intersil |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 32K EE 8-DIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.63V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
X5323, X5325
SPI Serial Memory
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write ? cell,
7
WPEN
6
FLB
5
WD1
4
WD0
3
BL1
2
BL0
1
WEL
0
WIP
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on th e SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the status of
the write enable latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
SFLB
WRDI/RFLB
RSDR
WRSR
READ
WRITE
INSTRUCTION FORMAT*
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
OPERATION
Set the write enable latch (enable write operations)
Set flag bit
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN and flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
WEL
0
1
1
1
STATUS REGISTER
WPEN
X
1
0
X
DEVICE PIN
WP
X
0
X
1
BLOCK
Protected Block
Protected
Protected
Protected
Protected
BLOCK
Unprotected Block
Protected
Writable
Writable
Writable
STATUS REGISTER
WPEN, BL0, BL1 WD0, WD1
Protected
Protected
Writable
Writable
7
FN8131.2
June 30, 2008
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