参数资料
| 型号： | X5323PI-4.5A |
| 厂商： | Intersil |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 32K EE 8-DIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.63V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
X5323, X5325
Pin Descriptions
PIN NUMBER
PIN NUMBER
(SOIC/PDIP)
1
TSSOP
1
PIN NAME
CS/WDI
PIN FUNCTION
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
9
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
4
8
7
7
14
13
V SS
V CC
RESET/
RESET
Ground
Supply Voltage
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V CC falls below the minimum V C C sens e level. It will remain active until V CC rises above
the minimum V CC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3 to 5,10 to 12
4
NC
No internal connections
FN8131.2
June 30, 2008
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| X5323PIZ | 功能描述:IC SUPERVISOR CPU 32K EE 8-DIP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 600 ms 电压 - 阀值:3.8V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) |
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| X5323PIZ-4.5A | 功能描述:IC SUPERVISOR CPU 32K EE 8-DIP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 600 ms 电压 - 阀值:3.8V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) |
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