参数资料
型号: X5328S8I-4.5A
厂商: Intersil
文件页数: 4/21页
文件大小: 0K
描述: IC SUPERVISOR CPU 32K EE 8-SOIC
标准包装: 100
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 4.63V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
X5328, X5329
PIN DESCRIPTION
Pin
Pin
(SOIC/PDIP)
1
TSSOP
1
Name
CS
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
4
8
7
7
14
13
V SS
V CC
RESET/
RESET
Ground
Supply Voltage
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V CC falls below the minimum V CC sense level. It
will remain active until V CC rises above the minimum V CC sense level for 200ms.
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
3-5,10-12
NC
No internal connections
PIN CONFIGURATION
14 Ld TSSOP
8 Ld SOIC/PDIP
CS
1
14
V CC
CS
1
8
V CC
SO
2
13
RESET/RESET
SO
2
X5328/29
7
RESET/RESET
NC
NC
3 12
4 X5328/29 11
NC
NC
WP
V CC
3
4
6
5
SCK
SI
NC
WP
5
6
10
9
NC
SCK
4
V SS
7
8
SI
FN8132.1
October 17, 2005
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