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参数资料
| 型号： | X5643P |
| 厂商： | Intersil |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | IC CPU SUPRV 64K EE RST LO 8DIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
X5643, X5645
Table 2. Block Protect Matrix
WREN CMD
Status Register
Device Pin
Block
Block
Status Register
WPEN, BL0, BL1
WEL
0
1
1
1
WPEN
X
1
0
X
WP#
X
0
X
1
Protected Block
Protected
Protected
Protected
Protected
Unprotected Block
Protected
Writable
Writable
Writable
WD0, WD1
Protected
Protected
Writable
Writable
The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When WEL = 1, the
latch is set HIGH and when WEL = 0 the latch is reset
Status Register Bits
Watchdog Time Out
LOW. The WEL bit is a volatile, read only bit. It can
be set by the WREN instruction and can be reset by
the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
WD1
0
0
1
1
WD0
0
1
0
1
(Typical)
1.4 seconds
600 milliseconds
200 milliseconds
disabled
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
Status
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power-up. This flag can be used by the sys-
tem to determine whether a reset occurs as a result of
a watchdog time out or power failure.
Register Bits
Array Addresses Protected
The nonvolatile WPEN bit is programmed using the
BL1
0
0
1
1
BL0
0
1
0
1
X5643/X5645
None
$1800-$1FFF
$1000-$1FFF
$0000-$1FFF
WRSR instruction. This bit works in conjunction with the
WP pin to provide an in-circuit programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
6
bits from inadvertent corruption.
In the locked state ( programmable ROM mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.
FN8135.1
July 18, 2005
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X5643P-4.5A | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5643S14 | 功能描述:IC CPU SUPRV 64K EE RST LO SO14 RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:标准传输延迟为 60 µs 电压 - 阀值:3V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:Digi-Reel® 其它名称:LM8364BALMF30DKR |
| X5643S14-1.8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5643S14-2.7 | 功能描述:IC CPU SUPRV 64K EE RST LO SO14 RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:标准传输延迟为 60 µs 电压 - 阀值:3V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:Digi-Reel® 其它名称:LM8364BALMF30DKR |
| X5643S14-2.7A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
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