参数资料
型号: X5649S14I-2.7A
厂商: Intersil
文件页数: 2/18页
文件大小: 0K
描述: IC SUPERVISOR CPU 64K EE 14-SOIC
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 高有效
复位超时: 最小为 100 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 管件
X5648, X5649
PIN CONFIGURATION
14-Lead SOIC
8-Lead PDIP
NC
1
14
NC
CS
1
8
V CC
CS
2
13
V CC
SO
WP
V SS
2
3
4
X5648/49
7
6
5
RESET/RESET
SCK
SI
CS
SO
WP
V SS
3
4
5
6
X5648/49
12
11
10
9
V CC
RESET/RESET
SCK
SI
NC
7
8
NC
PIN DESCRIPTION
Pin
Pin
(PDIP)
1
(SOIC)
2, 3
Name
CS
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
2
4
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
5
9
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
10
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
5
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
4
8
7
6
12, 13
11
V SS
V CC
RESET/
RESET
Ground
Supply Voltage
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V CC falls below the minimum V CC sense level. It will re-
mai n active until V CC rises above the minimum V CC sense level for 200ms. RE-
SET/RESET goes active if the watchdog timer is enabled and CS remains either
HIGH or LOW longer than the selectable watchdog time out period. A falling
edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
1, 7, 8, 14
2
NC
No internal connections
FN8136.0
March 17, 2005
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X5649S14I-2.7 IC SUPERVISOR CPU 64K EE 14-SOIC
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