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参数资料
| 型号： | X76F641WG |
| 厂商： | IC MICROSYSTEMS SDN BHD |
| 元件分类： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 8K X 8 FLASH 5V PROM, UUC |
| 封装： | ROHS COMPLIANT, WAFER |
| 文件页数： | 3/17页 |
| 文件大小： | 167K |
| 代理商： | X76F641WG |
X76F641
3
Figure 1. X76F641 Device Operation
Retry Counter
The X76F641 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
command must be used with a RESET password.
Device Protocol
The X76F641 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as a
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master will
always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F641 will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F641 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts are
inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used to
reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
The X76F641 will respond with an acknowledge after
recognition of a start condition and its slave address.
If
both the device and a write condition have been
selected, the X76F641 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
Reset Device Command
The reset device command is used to clear the retry
counter and reactivate the device. When the reset device
command is used prior to the retry counter overflow, the retry
counter is reset and no arrays or passwords are
affected. If the retry counter has overflowed, all memory
areas are cleared and all commands are blocked and the
retry counter is disabled. Issuing a valid reset device
command (with reset password) to the device resets and
re-enables the retry counter and re-enables the other
commands. Again, the passwords are not affected.
Reset Password Command
A reset password command will clear both arrays and set all
passwords to all zero.
LOAD COMMAND BYTE
LOAD 2 BYTE ADDRESS
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
READ/WRITE
DATA BYTES
7025 FM 03
Twc OR DATA ACK POLLING
相关PDF资料 |
PDF描述 |
|---|---|
| X76F641WG-2.0 | 4 Mbit Uniform Sector, Serial Flash Memory |
| X76F641XEG | 4 Mbit Uniform Sector, Serial Flash Memory |
| X76F641XEG-2.0 | 4 Mbit Uniform Sector, Serial Flash Memory |
| X76F641XG | 4 Mbit Uniform Sector, Serial Flash Memory |
| X76F641XG-2.0 | 4 Mbit Uniform Sector, Serial Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| X76F641WG-2.0 | 制造商:ICMIC 制造商全称:IC MICROSYSTEMS 功能描述:Secure Serial Flash |
| X76F641X | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:Secure SerialFlash |
| X76F641X-2.0 | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:Secure SerialFlash |
| X76F641XE | 制造商:ICMIC 制造商全称:IC MICROSYSTEMS 功能描述:Secure Serial Flash |
| X76F641XE-2.0 | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:Secure SerialFlash |
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