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参数资料
| 型号： | X80203V20I |
| 厂商： | Intersil |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY SEQUENCER 20TSSOP |
| 标准包装： | 75 |
| 应用： | 电源序列发生器 |
| 电源电压： | 0.95 V ~ 5.5 V |
| 电流 - 电源： | 2.5mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X80200, X80201, X80202, X80203, X80204
Functional Diagram
VDDH
18
V F B
17
DNC
16
GATE_M
15
GATE_H
14
VDDM 19
VDDL 20
SETV 1
REF 2
UVLO H
UVLO M
UVLO L
+
–
OSC
CHARGE
PUMP_M
CHARGE
PUMP_H
CHARGE
PUMP_L
CORE-UP-FIRST
CORE-DOWN-LAST
13 GATE_L
12 ENS
11 GATEH_EN
10 READY
A0 3
2-WIRE
INTERFACE
STATUS REGISTER
REMOTE SHUTDOWN REGISTER
9 SCL
4
GND
5
A1
6
A2
7
NC
8
SDA
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
NAME
SETV
REF
A0
GND
A1
A2
NC
SDA
SCL
READY
DESCRIPTION
Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL.
If unused connect to ground.
Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the
VFB pin and provides the threshold for turn on of the GATE_M output. Either a voltage source or external resistor divider can
be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH.
Slave address pin assignment. It has an Internal pull down resistor. (>10M ? typical)
Voltage Ground.
Slave address pin assignment. It has an Internal pull down resistor. (>10M ? typical)
Slave Address pin assignment. It has an Internal pull down resistor. (>10M ? typical)
No internal connections.
Serial bus data input/output pin.
Serial bus clock input pin.
READY Output Pin: This open-drain output pin goes LOW while VDDH is below UVLO H and remains LOW for t PURST after
VDDH goes above UVLO H . READY goes HIGH after t PURST .
11
GATEH_EN GATE_H Enable. When this pin is HIGH and VDDH > UVLO H the charge pump of the GATE_H pin turns on and the output
drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE_H output is LOW. An external RC time delay
can be connected between the enable signal and this pin to delay the GATE_H turn on.
12
13
14
15
16
17
18
19
20
ENS
GATE_L
GATE_H
GATE_M
DNC
VFB
VDDH
VDDM
VDDL
Enable Sequence. This pin is used for time-based power sequencing of supplies VDDM and VDDL. If unused, connect to ground.
GATE_L Output: This output is connected to the gate of an (external) Power Switch “L”. The GATE_L pin is driven HIGH when
charge pump L is enabled and pulled LOW when the charge pump is disabled.
GATE_H Output: This output is connected to the gate of a (external) Power Switch “H”. The GATE_H pin driven HIGH when
charge pump H is enabled and pulled LOW when the charge pump is disabled.
GATE_M Output: This output is connected to the gate of a (external) Power Switch “M”. The GATE_M pin driven HIGH when
charge pump M is enabled and pulled LOW when the charge pump is disabled.
Do not connect (must be left floating).
Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turned-
on supply. If unused, connect to ground.
Primary supply voltage (typically 5V).
Monitored Supply Voltage “M” input.
Monitored Supply Voltage “L” input.
2
FN8154.0
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相关代理商/技术参数 |
参数描述 |
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| X8037QC | 制造商:ABRACON 制造商全称:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
| X8037QCL | 制造商:ABRACON 制造商全称:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
| X80386DX WAF | 制造商:Intel 功能描述: |
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