参数资料
| 型号： | X9259UV24IZT1 |
| 厂商： | Intersil |
| 文件页数： | 18/21页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL QUAD 50K OHM 24TSSOP |
| 标准包装： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 4 |
| 温度系数： | 标准值 ±300 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | X9259UV24IZT1DKR |
6
FN8169.5
April 13, 2007
Serial Interface
The X9259 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provide the clock for both
transmit and receive operations. Therefore, the X9259
operates as a slave device in all applications.
All 2-wire interface operations must begin with a START,
followed by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions. See
Figure 2. On power up of the X9259 the SDA pin is in the
input mode.
START Condition
All commands to the X9259 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9259 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met. See
Figure 2.
STOP Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. See Figure 2. The STOP condition is also
used to place the device into the Standby Power mode after
a Read sequence. A STOP condition can only be issued
after the transmitting device has released the bus.
Acknowledge
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data. See Figure 3.
The X9259 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Instruction Byte.
The X9259 also responds with an ACK after receiving a Data
Byte after a Write Instruction.
A valid Identification Byte contains the Device Type Identifier
0101, as the four MSBs, and the Device Address bits
matching the logic states of pins A3, A2, A1, and A0, as the
four LSBs. See Figure 4.
In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
During the internal non-volatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an
ACK after Identification bytes.
X9259
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| X9259UV24Z-2.7 | 功能描述:IC XDCP QUAD 256TAP 50K 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:XDCP™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 接片:256 电阻（欧姆）:100k 电路数:2 温度系数:标准值 35 ppm/°C 存储器类型:易失 接口:6 线串行（芯片选择，递增，增/减） 电源电压:2.6 V ~ 5.5 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:14-TSSOP 包装:带卷 (TR) |
| X9260 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual Digitally-Controlled Potentiometers |
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