参数资料
型号: X9440WS24I
厂商: Intersil
文件页数: 17/21页
文件大小: 0K
描述: IC DUAL PROG COMP 10K 64TP SO24
标准包装: 30
系列: XDCP™
接片: 64
电阻(欧姆): 10k
电路数: 2
温度系数: 标准值 ±300 ppm/°C
存储器类型: 非易失
接口: 6 线 SPI(芯片选择,设备位址)
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC
包装: 管件
5
FN8200.0
March 28, 2005
REGISTER BIT DESCRIPTIONS
Wiper Counter Register (WCR)
WP0-WP5 identify wiper position.
Analog Control Register (ACR)
Shutdown
“1”
indicates power is connected to the voltage
comparator.
“0”
indicates power is not connected to the voltage
comparator.
Enable
“1”
indicates the output buffer of the voltage
comparator is enabled.
“0”
indicates the output buffer of the voltage
comparator is disabled.
Latch
“1”
indicates the output of the voltage comparator is
memorized or latched.
“0”
indicates the output of the voltage comparator is
not latched.
Userbits—available for user applications
Data Registers (DR, R0-R3)
{Refer to Memory Map, Figure 9}
INSTRUCTIONS AND PROGRAMMING
Identification (ID) Byte
The first byte sent to the X9440 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9440 this
is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0-A1 input pins.
The X9440 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9440 to successfully
continue the command sequence. The A0-A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots or two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 3.
Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four data registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four potenti-
ometers is to be affected by the instruction.
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four data registers
that is to be acted upon when a register oriented instruc-
tion is issued. The last two bits (P1 and P0) select which
one of the two potentiometers or which one of the two
voltage comparators is to be affected by the instruction.
0
WP5 WP4 WP3 WP2 WP1
WP0
(volatile)
(LSB)
00
User-
bit5
User-
bit4
User-
bit3
Latch Enable
Shut-
down
(volatile)
(LSB)
Wiper Position or Analog Control Data or User Data
(Nonvolatile)
1
00
0
A1
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
P1
P0
Pot Select
Register
Select
Instructions
X9440
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