参数资料
型号: X9520V20I-A
厂商: Intersil
文件页数: 3/29页
文件大小: 0K
描述: IC 3 DCP 2K EE LASR CTRL 20TSSOP
标准包装: 75
类型: 激光二极管控制器(光纤)
通道数: 3
电源电压: 2.7 V ~ 5.5 V
电流 - 电源: 1.5mA
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 管件
安装类型: 表面贴装
X9520
Pinout
X9520
(20 LD TSSOP)
TOP VIEW
R H2
R W2
R L2
V3
V3RO
MR
WP
SCL
SDA
V SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V1/VCC
V1RO
V2RO
V2
R L0
R W0
R H0
R H1
R W1
R L1
NOT TO SCALE
Pin Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NAME
R H2
R w2
R L2
V3
V3RO
MR
WP
SCL
SDA
Vss
R L1
R w1
R H1
R H0
R W0
R L0
V2
V2RO
FUNCTION
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the
V TRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to V SS when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V TRIP3 and goes LOW
when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”
resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin
(V1/VCC RESET Output pin). V1RO will remain HIGH for time t purst after MR has returned to it’s normally LOW state. The
reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock
feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed
in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin
uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input
buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the
V TRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to V SS when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than V TRIP2 , and goes LOW
when V2 is less than V TRIP2 . There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an
external “pull-up” resistor.
3
FN8206.2
August 20, 2007
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