参数资料
型号: X9530V14IT1
厂商: Intersil
文件页数: 24/28页
文件大小: 0K
描述: IC LASER DIODE CTRLR 14-TSSOP
标准包装: 2,500
类型: 激光二极管控制器(光纤)
通道数: 1
电源电压: 3 V ~ 5.5 V
电流 - 电源: 9mA
工作温度: -40°C ~ 100°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
安装类型: 表面贴装
X9530
D/A CONVERTER CHARACTERISTICS
All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the
recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. All bits in
control registers are “0” unless otherwise specified. 510 Ω , 0.1%, resistor connected between R1 and Vss, and another
between R2 and Vss unless otherwise specified. 400kHz TTL input at SCL unless otherwise specified. SDA pulled to Vcc
through an external 2k Ω resistor unless otherwise specified. 2-wire interface in “standby” (see notes 1 and 2 on page 22),
unless otherwise specified. WP, A0, A1, and A2 floating unless otherwise specified.
Symbol
IFS 00
IFS 01
IFS 10
IFS 11
Offset DAC
FSError DAC
DNL DAC
INL DAC
VISink
VISource
I OVER
I UNDER
t rDAC
TCO I1I2
Parameter
I1 or I2 full scale current, with external
resistor setting
I1 or I2 full scale current, with internal
low current setting option
I1 or I2 full scale current, with internal
middle current setting option
I1 or I2 full scale current, with internal
high current setting option
I1 or I2 D/A converter offset error
I1 or I2 D/A converter full scale error
I1 or I2 D/A converter
Differential Nonlinearity
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
I1 or I2 Sink Voltage Compliance
I1 or I2 Source Voltage Compliance
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
Temperataure coefficient of output
current I1 or I2 when using internal
resistor setting
Min
1.56
0.3
0.64
1
1
-2
-0.5
-1
1.2
0
5
Typ
1.58
0.4
0.85
1.3
±200
Max
1.6
0.5
1.06
1.6
1
2
0.5
1
Vcc
Vcc-1.2
0
0
30
Unit
mA
mA
mA
mA
LSB
LSB
LSB
LSB
V
V
μ A
μ A
μ s
ppm/
°C
Test Conditions / Notes
DAC input Byte = FFh,
Source or sink mode, V(I1)
and V(I2) are Vcc - 1.2V in
source mode and 1.2V in sink
mode.
See notes 1 and 2.
In this range the current at I1
or I2 vary < 1%
In this range the current at I1
or I2 vary < 1%
DAC input byte changing from
00h to FFh and vice
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
See note 3.
See Figure 5.
Bits I1FSO[1:0] | 00 2 or
Bits I2FSO[1:0] | 002,
VRMbit = “1”
Notes: 1. LSB is defined as
255
[ 23 x V(VRef) ]
divided by the resistance between R1 or R2 to Vss.
2. Offset DAC : The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError DAC : The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset DAC is subtracted from the measured value before calculating FSError DAC .
DNL DAC : The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL DAC .
INL DAC : The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
3. These parameters are periodically sampled and not 100% tested.
24
FN8211.1
November 11, 2005
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