- 您现在的位置：买卖IC网 > PDF目录376449 > X98024L128-3.3 (INTERSIL CORP) 240MHz Triple Video Digitizer with Digital PLL PDF资料下载
参数资料
| 型号： | X98024L128-3.3 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | 240MHz Triple Video Digitizer with Digital PLL |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封装： | 14 X 20 MM, MS-022, MQFP-128 |
| 文件页数： | 24/29页 |
| 文件大小： | 295K |
| 代理商： | X98024L128-3.3 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页
24
FN8220.0
June 6, 2005
.
Initialization
The X98024 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
Register 0x23 should be set to 0x78 to enable the DC
Restore function
Reset
The X98024 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HS
OUT
may sporadically lock to the wrong edge
of HSYNC
IN
. This will cause the HS
OUT
to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNC
IN
signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
HSYNC
IN
(to A and B)
PIXELCLK (A)
(Internal)
DATA
PRI
(A)
HS
OUT
(A)
DPLL Lock Edge
PIXELCLK = DATACLK Delay
CLKINV
IN
(A) = GND
D
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3
P
N-2
P
N-1
P
N
Analog Video In
(to A and B)
DATA
SEC
(A)
DATACLK (A)
D
0
D
2
D
N-3
D
N-1
CLKINV
IN
(B) = GND
D
D
1
D
3
D
N-2
D
N
PIXELCLK (B)
(Internal)
DATA
PRI
(B)
HS
OUT
(B)
DATA
SEC
(B)
DATACLK (B)
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
X98024
相关PDF资料 |
PDF描述 |
|---|---|
| X98024L128-3.3-Z | 240MHz Triple Video Digitizer with Digital PLL |
| XC145481 | 3 V PCM Codec-Filter |
| XC145481DW | 3 V PCM Codec-Filter |
| XC145481P | 3 V PCM Codec-Filter |
| XC145481SD | 3 V PCM Codec-Filter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| X98027 | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:PRELIMINARY INFORMATION |
| X98027_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:275MHz Triple Video Digitizer with Digital PLL |
| X98027L128-3.3 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:275MHz Triple Video Digitizer with Digital PLL |
| X98027L128-3.3-Z | 功能描述:IC TRPL VID DIGITIZER 128MQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 标准包装:250 系列:- 类型:电平移位器 应用:LCD 电视机/监控器 安装类型:表面贴装 封装/外壳:28-WFQFN 裸露焊盘 供应商设备封装:28-WQFN（4x4）裸露焊盘 包装:带卷 (TR) 其它名称:296-32523-2TPS65198RUYT-ND |
| X-98-499 | 制造商:Brady Corporation 功能描述:Labels External Width:1" |
发布紧急采购，3分钟左右您将得到回复。