参数资料
型号: XA2C32A-7VQG44Q
厂商: Xilinx Inc
文件页数: 4/14页
文件大小: 0K
描述: IC CPLD 32MCELL 33 I/O 44-VQFP
产品培训模块: CoolRunner-II CPLD Starter Kit
标准包装: 160
系列: CoolRunner II
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 5.5ns
电压电源 - 内部: 1.7 V ~ 1.9 V
逻辑元件/逻辑块数目: 2
宏单元数: 32
门数: 750
输入/输出数: 33
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 44-TQFP
供应商设备封装: 44-VQFP(10x10)
包装: 托盘
XA2C32A CoolRunner-II Automotive CPLD
12
DS552 (v1.1) May 5, 2007
Product Specification
R
Figure 6: VQ44 Package
CoolRunner-II Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applica-
tions:
1. Use a monotonic, fast ramp power supply to power up
CoolRunner-II . A VCC ramp time of less than 1 ms is
required.
2. Do not float I/O pins during device operation. Floating
I/O pins can increase ICC as input buffers will draw
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
I/O pins should be appropriately terminated with
bus-hold or pull-up. Unused I/Os can also be configured
as CGND (programmable GND).
3. Do not drive I/O pins without VCC/VCCIO powered.
4. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to VCC. Consequently, this
will give the brightest solution.
5. Avoid pull-down resistors. Always use external pull-up
resistors if external termination is required. This is
because the CoolRunner-II Automotive CPLD, which
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
6. Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
a. The current flow can go into VCCIO and affect a user
voltage regulator.
b. It can also increase undesired leakage current
associated with the device.
c. If done for too long, it can reduce the life of the
device.
7. Do not rely on the I/O states before the CPLD
configures. During power up, the CPLD I/Os may be
affected by internal or external signals.
8. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
9. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO should comply with the IEEE 1149.1. All Xilinx
CPLDs have internal weak pull-ups on TDI, TMS, and
TCK.
VQG44
Top View
I/O(1)
I/O(3)
I/O
VCCIO2
GND
TDO
I/O
(2)
I/O
(2)
I/O
V
AU
X
I/O
(1)
I/O
V
CC
I/O
GND
I
I/O
I/O(2)
I/O
GND
I/O
VCCIO1
I/O
TDI
TMS
TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
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