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| 型号： | XA9572XL-15VQG44I |
| 厂商： | Xilinx Inc |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 3.3V 72MCELL 44-VQFP |
| 标准包装： | 160 |
| 系列： | XA9500XL XA |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 4 |
| 宏单元数： | 72 |
| 门数： | 1600 |
| 输入/输出数： | 34 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-VQFP（10x10） |
| 包装： | 托盘 |
XA9500XL Automotive CPLD Product Family
2
DS108-1 (v1.7) April 3, 2007
Product Specification
R
Absolute Maximum Ratings(1,2)
Recommended Operating Conditions
Quality and Reliability Characteristics
Table 2: XA9500XL Packages and User I/O Pins (not including four dedicated JTAG pins)
Device
VQG44
VQG64
TQG100
CSG144
XA9536XL
34
--
XA9572XL
34
52
72
--
XA95144XL
--
117
Symbol
Description
Min.
Max.
Units
VCC
Supply voltage relative to GND
–0.5
4.0
V
VIN
Input voltage relative to GND(3)
–0.5
5.5
V
VTS
Voltage applied to 3-state output(3)
–0.5
5.5
V
TSTG
Storage temperature (ambient)(4)
–65
+150
oC
TJ
Junction temperature
-
+125
oC
Notes:
1.
All automotive customers are required to set the Macrocell Power Setting to low, and set Logic Optimization to density.
2.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
4.
For soldering guidelines, see the Package Information on the Xilinx website.
Symbol
Parameter
Min
Max
Units
TA
Ambient temperature
I-Grade
–40
+85
°C
Q-Grade
–40
+105
°C
VCCINT
Supply voltage for internal logic and input buffers
3.0
3.6
V
VCCIO
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.3
2.7
V
VIL
Low-level input voltage
0
0.80
V
VIH
High-level input voltage
2.0
5.5
V
VO
Output voltage
0
VCCIO
V
Symbol
Parameter
Min
Max
Units
TDR
Data Retention
20
-
Years
NPE
Program/erase cycles (Endurance) @ TA = 70°C
10,000
-
Cycles
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