- 您现在的位置：买卖IC网 > PDF目录19474 > XC2C256-6FTG256C (Xilinx Inc)IC CR-II CPLD 256MCELL 256-FTBGA PDF资料下载
参数资料
| 型号： | XC2C256-6FTG256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 1/16页 |
| 文件大小： | 0K |
| 描述： | IC CR-II CPLD 256MCELL 256-FTBGA |
| 标准包装： | 90 |
| 系列： | CoolRunner II |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 5.7ns |
| 电压电源 - 内部： | 1.7 V ~ 1.9 V |
| 逻辑元件/逻辑块数目： | 16 |
| 宏单元数： | 256 |
| 门数： | 6000 |
| 输入/输出数： | 184 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-FTBGA |
| 包装： | 托盘 |
| 配用： | 122-1573-ND - KIT STARTER COOLRUNNER-II LP/LC 122-1512-ND - KIT DESIGN CPLD W/BATT HOLDER |
DS090 (v3.1) September 11, 2008
1
Product Specification
2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
-
Industry’s fastest low power CPLD
-
Densities from 32 to 512 macrocells
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation — 1.5V to 3.3V
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
On-The-Fly Reconfiguration (OTF)
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt trigger input (per pin)
-
Multiple I/O banks on all devices
-
Unsurpassed low power management
DataGATE external signal control
-
Flexible clocking modes
Optional DualEDGE triggered registers
Clock divider (
÷ 2,4,6,8,10,12,14,16)
CoolCLOCK
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Abundant product term clocks, output enables and
set/resets
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional bus-hold, 3-state or weak pullup on select
I/O pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
-
SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
-
Hot pluggable
PLA architecture
-
Superior pinout retention
-
100% product term routability across function block
Wide package availability including fine pitch:
-
Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and QFN packages
-
Pb-free available for all packages
Design entry/verification using Xilinx and industry
standard CAE tools
Free software support for all densities using Xilinx
WebPACK tool
Industry leading nonvolatile 0.18 micron CMOS
process
-
Guaranteed 1,000 program/erase cycles
-
Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE 4.1i WebPACK tool.
Additional details can be found in Further Reading,
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
0
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
00
Product Specification
R
Table 1: CoolRunner-II CPLD Family Parameters
XC2C32A
XC2C64A
XC2C128
XC2C256
XC2C384
XC2C512
Macrocells
32
64
128
256
384
512
Max I/O
33
64
100
184
240
270
TPD (ns)
3.8
4.6
5.7
7.1
TSU (ns)
1.9
2.0
2.4
2.9
2.6
TCO (ns)
3.7
3.9
4.2
4.5
5.8
FSYSTEM1 (MHz)
323
263
244
256
217
179
相关PDF资料 |
PDF描述 |
|---|---|
| ABM36DRKS | CONN EDGECARD 72POS DIP .156 SLD |
| TAP685M035SRW | CAP TANT 6.8UF 35V 20% RADIAL |
| VE-B1T-CX-B1 | CONVERTER MOD DC/DC 6.5V 75W |
| NMH1209SC | CONV DC/DC 2W 12VIN 9VOUT SIP DL |
| ADSP-BF538BBCZ-5F8 | IC DSP CTLR 16BIT 316CSPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2C256-6PQ208C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 6K GATES 256 MCRCLLS 450MHZ 0.18UM 1.8V 2 - Trays 制造商:Xilinx 功能描述:IC CPLD 256MC 5.7NS 208PQFP 制造商:Xilinx 功能描述:IC CR-II CPLD 256MCELL 208PQFP |
| XC2C256-6PQ208CES | 制造商:Xilinx 功能描述: |
| XC2C256-6PQG208C | 功能描述:IC CR-II CPLD 256MCELL 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:CoolRunner II 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC2C256-6TQ144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 6K GATES 256 MCRCLLS 450MHZ 0.18UM 1.8V 1 - Trays 制造商:Xilinx 功能描述:IC CPLD 256MC 5.7NS 144QFP 制造商:Xilinx 功能描述:IC CR-II CPLD 256MCELL 144-QFP |
| XC2C256-6TQG144C | 功能描述:IC CR-II CPLD 256MCELL 144-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:CoolRunner II 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
发布紧急采购，3分钟左右您将得到回复。