参数资料
型号: XC2S100E-6PQ208C
厂商: Xilinx Inc
文件页数: 100/108页
文件大小: 0K
描述: IC FPGA 1.8V 600 CLB'S 208-PQFP
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 24
系列: Spartan®-IIE
LAB/CLB数: 600
逻辑元件/单元数: 2700
RAM 位总计: 40960
输入/输出数: 146
门数: 100000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
其它名称: 122-1207
DS077-4 (v3.0) August 9, 2013
91
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L188P
7
L8
XC2S400E
-
I/O, L188P_Y
I/O, L188P
I/O, L188N
7
L7
XC2S400E
-
I/O, L188N_Y
I/O, L188N
I/O, L187P
7
L6
XC2S600E
-
I/O, L187P
I/O, L187P_Y
I/O, L187N
7
L5
XC2S600E
-
I/O, L187N
I/O, L187N_Y
I/O
7
L3
-
I/O
I/O, L186P
7
L2
XC2S600E
-
I/O, L186P
I/O, L186P_Y
I/O, L186N
7
L1
XC2S600E
-
I/O, L186N
I/O, L186N_Y
I/O
7
M9
-
I/O
I/O, L185P
7
M8
XC2S600E
-
I/O, L185P
I/O, L185P_Y
I/O, L185N
7
M7
XC2S600E
-
I/O, L185N
I/O, L185N_Y
I/O, VREF Bank 7,
L184P_YY
7
M6
All
I/O, VREF Bank 7,
L184P_YY
I/O, VREF Bank 7,
L184P_YY
I/O, L184N_YY
7
M5
All
-
I/O, L184N_YY
I/O
7
M4
-
I/O
I/O, L183P_YY
7
M2
All
-
I/O, L183P_YY
I/O, L183N_YY
7
M1
All
-
I/O, L183N_YY
I/O
7
N9
-
I/O
I/O, L182P
7
N8
XC2S400E
-
I/O, L182P_Y
I/O, L182P
I/O, L182N
7
N7
XC2S400E
-
I/O, L182N_Y
I/O, L182N
I/O, VREF Bank 7,
L181P
7
N6
XC2S600E
All
I/O, VREF Bank 7,
L181P
I/O, VREF Bank 7,
L181P_Y
I/O, L181N
7
N5
XC2S600E
-
I/O, L181N
I/O, L181N_Y
I/O
7
N4
-
I/O
I/O, L180P_YY
7
N3
All
-
I/O, L180P_YY
I/O, L180N_YY
7
N2
All
-
I/O, L180N_YY
I/O
7
N1
-
I/O
I/O, L179P_YY
7
P1
All
-
I/O, L179P_YY
I/O (IRDY), L179N_YY
7
P2
All
-
I/O (IRDY),
L179N_YY
I/O (IRDY), L179N_YY
I/O (TRDY), L178P
6
P3
XC2S600E
-
I/O (TRDY)
I/O (TRDY), L178P_Y
I/O, L178N
6
P4
XC2S600E
-
I/O, L178N_Y
I/O, L177P
6
P5
XC2S600E
-
I/O, L177P_Y
I/O, L177N
6
P6
XC2S600E
-
I/O
I/O, L177N_Y
I/O
6
P7
-
I/O
I/O, L176P
6
P8
XC2S600E
-
I/O, L176P
I/O, L176P_Y
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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