参数资料
| 型号： | XC2S150E-6FT256I |
| 厂商： | Xilinx Inc |
| 文件页数： | 14/108页 |
| 文件大小： | 0K |
| 描述： | SPARTAN FPGA 150000 GATE 1.8V |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 90 |
| 系列： | Spartan®-IIE |
| LAB/CLB数： | 864 |
| 逻辑元件/单元数： | 3888 |
| RAM 位总计： | 49152 |
| 输入/输出数： | 182 |
| 门数： | 150000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-FTBGA |
| 其它名称： | Q1280323 |
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DS077-2 (v3.0) August 9, 2013
13
Product Specification
Spartan-IIE FPGA Family: Functional Description
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Configurable Logic Block
The basic building block of the Spartan-IIE FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. The output from the func-
tion generator in each LC drives the CLB output or the
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-
tains four LCs, organized in two similar slices; a single slice
is shown in Figure 6.
In addition to the four basic LCs, the Spartan-IIE FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-IIE FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit syn-
chronous RAM. Furthermore, the two LUTs within a slice
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-IIE FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in applica-
tions such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-IIE FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S150E-6FTG256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S150E-6FTG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S150E-6PQ208C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S150E-6PQ208C0818 | 制造商:Xilinx 功能描述: |
| XC2S150E-6PQ208I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
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