参数资料
| 型号： | XC2S30-5CS144I |
| 厂商： | Xilinx Inc |
| 文件页数： | 11/99页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V I-TEMP 144-CSBGA |
| 标准包装： | 198 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 216 |
| 逻辑元件/单元数： | 972 |
| RAM 位总计： | 24576 |
| 输入/输出数： | 92 |
| 门数： | 30000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-TFBGA，CSPBGA |
| 供应商设备封装： | 144-LCSBGA（12x12） |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
19
R
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low. At this time, the user can
delay configuration by holding either PROGRAM or INIT
Low, which causes the device to remain in the memory
clearing phase. Note that the bidirectional INIT line is
driving a Low logic level during memory clearing. To avoid
contention, use an open-drain driver to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the
configuration data are discussed in the sections treating the
configuration modes individually. The sequence of
operations necessary to load configuration data using the
serial modes is shown in Figure 14. Loading data using the
Slave Parallel mode is shown in Figure 19, page 25.
CRC Error Checking
During the loading of configuration data, a CRC value
embedded in the configuration file is checked against a
CRC value calculated within the FPGA. If the CRC values
do not match, the FPGA drives INIT Low to indicate that a
frame error has occurred and configuration is aborted.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See "Clearing
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the
configuration data, initiates the sequence.
During start-up, the device performs four operations:
1.
The assertion of DONE. The failure of DONE to go High
may indicate the unsuccessful loading of configuration
data.
2.
The release of the Global Three State net. This
activates I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-down resistors present.
3.
Negates Global Set Reset (GSR). This allows all
flip-flops to change state.
4.
The assertion of Global Write Enable (GWE). This
allows all RAMs and flip-flops to change state.
Notes: (referring to waveform above:)
1.
Before configuration can begin, VCCINT must be greater than 1.6V and VCCO Bank 2 must be greater than 1.0V.
Figure 12: Configuration Timing on Power-Up
DS001_12_102301
TPOR
TPL
TICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
PROGRAM
INIT
VCC(1)
.
Symbol
Description
Min
Max
TPOR
Power-on reset
-
2 ms
TPL
Program latency
-
100
μs
TICCK
CCLK output delay (Master Serial mode only)
0.5
μs4 μs
TPROGRAM
Program pulse width
300 ns
-
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