参数资料
型号: XC2S600E-6FGG456C
厂商: Xilinx Inc
文件页数: 98/108页
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 600K 456FBGA
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 60
系列: Spartan®-IIE
LAB/CLB数: 3456
逻辑元件/单元数: 15552
RAM 位总计: 294912
输入/输出数: 329
门数: 600000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 456-BBGA
供应商设备封装: 456-FBGA
其它名称: 122-1332
DS077-2 (v3.0) August 9, 2013
9
Product Specification
2001-2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Architectural Description
Spartan-IIE FPGA Array
The Spartan-IIE user-programmable gate array, shown in
Figure 3, is composed of five major configurable elements:
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
As can be seen in Figure 3, the CLBs form the central logic
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Values stored in static memory cells control all the configu-
rable logic elements and interconnect resources. These val-
ues load into the memory cells on power-up, and can reload
if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
Spartan-IIE FPGA Family:
Functional Description
DS077-2 (v3.0) August 9, 2013
0
Product Specification
R
Figure 3: Basic Spartan-IIE Family FPGA Block Diagram
DLL
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
I/O LOGIC
CLBs
DS077_01_052102
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