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Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
25
Table 27: Enhanced Pipelined Multiplier Switching Characteristics
Description
Symbol
Speed Grade
Units
-6
-5
-4
Setup and Hold Times Before/After Clock
Data Inputs
TMULIDCK/TMULCKID
3.00/0.00
3.45/0.00
3.89/0.00
ns, Max
Clock Enable
TMULIDCK_CE/TMULCKID_CE
0.72/0.00
0.80/0.00
0.86/0.00
ns, Max
Reset
TMULIDCK_RST/TMULCKID_RST
0.72/0.00
0.80/0.00
0.86/0.00
ns, Max
Clock to Output Pin
Clock to Pin 35
TMULTCK1_P35
3.05
3.25
3.74
ns, Max
Clock to Pin 34
TMULTCK1_P34
2.95
3.14
3.61
ns, Max
Clock to Pin 33
TMULTCK1_P33
2.85
3.04
3.49
ns, Max
Clock to Pin 32
TMULTCK1_P32
2.76
2.93
3.37
ns, Max
Clock to Pin 31
TMULTCK1_P31
2.66
2.82
3.25
ns, Max
Clock to Pin 30
TMULTCK1_P30
2.56
2.72
3.12
ns, Max
Clock to Pin 29
TMULTCK1_P29
2.47
2.61
3.00
ns, Max
Clock to Pin 28
TMULTCK1_P28
2.37
2.50
2.88
ns, Max
Clock to Pin 27
TMULTCK1_P27
2.27
2.40
2.75
ns, Max
Clock to Pin 26
TMULTCK1_P26
2.17
2.29
2.63
ns, Max
Clock to Pin 25
TMULTCK1_P25
2.08
2.18
2.51
ns, Max
Clock to Pin 24
TMULTCK1_P24
1.98
2.07
2.38
ns, Max
Clock to Pin 23
TMULTCK1_P23
1.88
1.97
2.26
ns, Max
Clock to Pin 22
TMULTCK1_P22
1.79
1.86
2.14
ns, Max
Clock to Pin 21
TMULTCK1_P21
1.69
1.75
2.02
ns, Max
Clock to Pin 20
TMULTCK1_P20
1.59
1.65
1.89
ns, Max
Clock to Pin 19
TMULTCK1_P19
1.50
1.54
1.77
ns, Max
Clock to Pin 18
TMULTCK1_P18
1.40
1.43
1.65
ns, Max
Clock to Pin 17
TMULTCK1_P17
1.30
1.33
1.52
ns, Max
Clock to Pin 16
TMULTCK1_P16
1.20
1.22
1.40
ns, Max
Clock to Pin 15
TMULTCK1_P15
1.11
1.28
ns, Max
Clock to Pin 14
TMULTCK1_P14
1.01
1.00
1.15
ns, Max
Clock to Pin 13
TMULTCK1_P13
0.91
1.00
1.15
ns, Max
Clock to Pin 12
TMULTCK1_P12
0.91
1.00
1.15
ns, Max
Clock to Pin 11
TMULTCK1_P11
0.91
1.00
1.15
ns, Max
Clock to Pin 10
TMULTCK1_P10
0.91
1.00
1.15
ns, Max
Clock to Pin 9
TMULTCK1_P9
0.91
1.00
1.15
ns, Max
Clock to Pin 8
TMULTCK1_P8
0.91
1.00
1.15
ns, Max
Clock to Pin 7
TMULTCK1_P7
0.91
1.00
1.15
ns, Max
Clock to Pin 6
TMULTCK1_P6
0.91
1.00
1.15
ns, Max
Clock to Pin 5
TMULTCK1_P5
0.91
1.00
1.15
ns, Max
Clock to Pin 4
TMULTCK1_P4
0.91
1.00
1.15
ns, Max
Clock to Pin 3
TMULTCK1_P3
0.91
1.00
1.15
ns, Max
Clock to Pin 2
TMULTCK1_P2
0.91
1.00
1.15
ns, Max
Clock to Pin 1
TMULTCK1_P1
0.91
1.00
1.15
ns, Max
Clock to Pin 0
TMULTCK1_P0
0.91
1.00
1.15
ns, Max