参数资料
型号: XC3042A-7VQ100C
厂商: Xilinx Inc
文件页数: 60/76页
文件大小: 0K
描述: IC FIELD PROG GATE ARRAY 100 PIN
产品变化通告: Product Discontinuation 27/Apr/2010
标准包装: 1
系列: XC3000A/L
LAB/CLB数: 144
RAM 位总计: 30784
输入/输出数: 82
门数: 3000
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 100-TQFP
供应商设备封装: 100-VQFP(14x14)
R
November 9, 1998 (Version 3.1)
7-65
XC3000 Series Field Programmable Gate Arrays
7
XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package
types, with pin counts from 44 to 208.
Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology.
Most package types are also offered with different chips to accommodate design changes without the need for PC board
changes.
Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package.
In some cases, the chip has more pads than there are pins on the package, as indicated by the information (“unused” pads)
below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified
propagation delays and set-up times are acceptable.
In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected
(n.c.), as shown above the line in the following table.
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Peripheral mode and Master Parallel mode are not supported in the PC44 package
Pin No.
XC3030A
Pin No.
XC3030A
1GND
23
GND
2
I/O
24
I/O
3
I/O
25
I/O
4
I/O
26
XTL2(IN)-I/O
5
I/O
27
RESET
6
I/O
28
DONE-PGM
7PWRDWN
29
I/O
8
TCLKIN-I/O
30
XTL1(OUT)-BCLK-I/O
9
I/O
31
I/O
10
I/O
32
I/O
11
I/O
33
I/O
12
VCC
34
VCC
13
I/O
35
I/O
14
I/O
36
I/O
15
I/O
37
I/O
16
M1-RDATA
38
DIN-I/O
17
M0-RTRIG
39
DOUT-I/O
18
M2-I/O
40
CCLK
19
HDC-I/O
41
I/O
20
LDC-I/O
42
I/O
21
I/O
43
I/O
22
INIT-I/O
44
I/O
Product Obsolete or Under Obsolescence
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