参数资料
| 型号： | XC3042L-8VQ100I |
| 厂商： | Xilinx Inc |
| 文件页数： | 8/76页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V I-TEMP 100-VQFP |
| 产品变化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 标准包装： | 90 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 144 |
| RAM 位总计： | 30784 |
| 输入/输出数： | 82 |
| 门数： | 3000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
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R
XC3000 Series Field Programmable Gate Arrays
7-18
November 9, 1998 (Version 3.1)
Crystal Oscillator
Figure 18 also shows the location of an internal high speed
inverting amplifier that may be used to implement an
on-chip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the oscilla-
tor is configured and connected as a signal source, two
special user IOBs are also configured to connect the oscil-
lator amplifier with external crystal oscillator components
as shown in Figure 19. A divide by two option is available to
assure symmetry. The oscillator circuit becomes active
early in the configuration process to allow the oscillator to
stabilize. Actual internal connection is delayed until com-
pletion of configuration. In Figure 19 the feedback resistor
R1, between the output and input, biases the amplifier at
threshold. The inversion of the amplifier, together with the
R-C networks and an AT-cut series resonant crystal, pro-
duce the 360-degree phase shift of the Pierce oscillator. A
series resistor R2 may be included to add to the amplifier
output impedance when needed for phase-shift control,
crystal resistance matching, or to limit the amplifier input
swing to control clipping at large amplitudes. Excess feed-
back voltage may be corrected by the ratio of C2/C1. The
amplifier is designed to be used from 1 MHz to about
one-half the specified CLB toggle frequency. Use at fre-
quencies below 1 MHz may require individual characteriza-
tion with respect to a series resistance. Crystal oscillators
above 20 MHz generally require a crystal which operates in
a third overtone mode, where the fundamental frequency
must be suppressed by an inductor across C2, turning this
parallel resonant circuit to double the fundamental crystal
frequency, i.e., 2/3 of the desired third harmonic frequency
network. When the oscillator inverter is not used, these
IOBs and their package pins are available for general user
I/O.
Alternate
Clock Buffer
XTAL1
XTAL2
(IN)
R1
R2
Y1
C1
C2
Internal
External
R1
R2
C1, C2
Y1
Suggested Component Values
0.5 – 1 M
0 – 1 k
(may be required for low frequency, phase
shift and/or compensation level for crystal Q)
10 – 40 pF
1 – 20 MHz AT-cut parallel resonant
X7064
68 PIN
PLCC
47
43
84 PIN
PLCC
57
53
PGA
J11
L11
132 PIN
PGA
P13
M13
160 PIN
PQFP
82
76
XTAL 1 (OUT)
XTAL 2 (IN)
100 PIN
CQFP
67
61
PQFP
82
76
164 PIN
CQFP
105
99
44 PIN
PLCC
30
26
175 PIN
PGA
T14
P15
208 PIN
PQFP
110
100
176 PIN
TQFP
91
85
D
Q
Figure 19: Crystal Oscillator Inverter. When activated, and by selecting an output network for its buffer, the crystal
oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
Product Obsolete or Under Obsolescence
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