参数资料
型号: XC3S200A-5FGG320C
厂商: Xilinx Inc
文件页数: 2/2页
文件大小: 0K
描述: IC SPARTAN-3A FPGA 200K 320-FBGA
产品培训模块: Extended Spartan 3A FPGA Family
标准包装: 84
系列: Spartan®-3A
LAB/CLB数: 448
逻辑元件/单元数: 4032
RAM 位总计: 294912
输入/输出数: 248
门数: 200000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 320-BGA
供应商设备封装: 320-FBGA(19x19)
其它名称: 122-1581
XC3S200A-5FGG320C-ND
Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: 408-559-7778
Fax: 408-559-7114
Web: www.xilinx.com
Europe Headquarters
Xilinx Ireland
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Ireland
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Phone +81-36744-7777
Web: japan.xilinx.com
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Web: www.xilinx.com
www.xilinx.com
Copyright 2OO7 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated
brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of
their respective owners
Printed in U.S.A. PN 2010
Industry’s first 90nm FPGA Electronic Serial Numbering
Each FPGA includes a permanent unique Device DNA serial number that can be used to
safeguard both hardware and software IP. It is ideal for tracking production serial numbers,
product registrations and system ID. Customers have complete flexibility in implementing
custom algorithms for the security solutions that can significantly deter reverse-engineering,
cloning and overbuilding.
Widest Support for I/O Standards
The Spartan-3A FPGA is especially suitable for display devices supporting both TMDS and
PPDS standards. With support for 26 popular single-ended and differential signaling stan-
dards including TMDS, PPDS, SSTL3 Class I & II, full hot-swap compliance, and pre-engi-
neered interface IP solutions such as PCI, PCI Express, USB, Firewire, CAN, SPI, I2C, etc, the
Spartan-3A platform provides an industry-leading connectivity solution.
Comprehensive Configuration Capabilities
The Spartan-3A platform features enhanced Multi-Boot capability with watchdog timer for
guaranteed “golden” configuration. This enables intelligent recovery from configuration
errors and improves field upgradeability.
Flexible Power-Management Modes
A new Suspend mode provides a very flexible and effective way to preserve power. In this
mode, the power is comparable to quiescent current, and the configuration data as well as
flip-flop and RAM values are maintained. It also includes a fast wake-up mechanism and sys-
tem level synchronization across time domains.
Dynamic Input Delay
Selecting delay-length for both registered and combinatorial inputs allows for precise timing
relationship adjustment between clock and data. Combinatorial input delay can now also be
dynamically changed through the interconnect. Source synchronous designs will significantly
benefit from this feature.
Take the Next Step
Visit our website www.xilinx.com/spartan3a or call your local sale office or distributor for
more information about Spartan-3A FPGAs. To start your design immediately, download
your free ISE WebPACKTM design tools at www.xilinx.com/ise. To begin evaluating Spartan-3A
FPGAs, order your hardware development board at www.xilinx.com/s3astarter
Spartan-3A FPGA Platform
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
System Gates
50K
200K
400K
700K
1400K
Logic Cells
1,584
4,032
8,064
13,248
25,344
Dedicated Multipliers
3
16
20
32
Block RAM Blocks
3
16
20
32
Block RAM Bits
54K
288K
360K
576K
Distributed RAM Bits
11K
28K
56K
92K
176K
DCMs
2
4
8
I/O Standards
26
Max Differential I/O
64
112
142
165
227
Max Single Ended I/O
144
248
311
372
502
Package and I/O Offerings
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
TQ144 20 x 20 mm
108
FT256 17 x 17 mm
144
195
FG320 19 x 19 mm
248
251
FG400 21 x 21 mm
311
FG484 23 x 23 mm
372
375
FG676 27 x 27 mm
502
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