参数资料
| 型号： | XC4003E-3PQ100I |
| 厂商： | Xilinx Inc |
| 文件页数： | 33/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 5V 3-SPD 100-PQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 100 |
| 逻辑元件/单元数： | 238 |
| RAM 位总计： | 3200 |
| 输入/输出数： | 77 |
| 门数： | 3000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
May 14, 1999 (Version 1.6)
6-43
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 41 on page 44 is a diagram of the XC4000 Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
XC4000 Series devices can also be congured through the
boundary scan logic. See “Readback” on page 55.
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single ip-op
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specied using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
corresponding
pins
(BSCAN.TDO1
and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
D
EC
Q
M
QL
rd
M
DELAY
M M
Input Clock IK
I - capture
I - update
GLOBAL
S/R
FLIP-FLOP/LATCH
INVERT
S/R
Input Data 1 I1
Input Data 2 I2
X5792
PAD
VCC
SLEW
RATE
PULL
UP
M
OUT
SEL
D
EC
Q
rd
M
INVERT
OUTPUT
M
INVERT
S/R
Ouput Clock OK
Clock Enable
Ouput Data O
O - update
Q - capture
O - capture
Boundary
Scan
M
EXTEST
TS - update
TS - capture
3-State TS
sd
TS INV
OUTPUT
TS/OE
PULL
DOWN
INPUT
Boundary
Scan
Boundary
Scan
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71V632ZS5PFG | IC SRAM 2MBIT 5NS 100TQFP |
| IDT7164L20YGI | IC SRAM 64KBIT 20NS 28SOJ |
| XC4003E-3PG120I | IC FPGA I-TEMP 5V 3-SPD 120-CPGA |
| IDT71V3559S85PFG | IC SRAM 4MBIT 85NS 100TQFP |
| IDT71V3559S80PFG | IC SRAM 4MBIT 80NS 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4003E-3VQ100C | 功能描述:IC FPGA C-TEMP 5V 3SPD 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC4003E-3VQ100I | 功能描述:IC FPGA I-TEMP 5V 3SPD 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC4003E4PC84C | 制造商:XILINX 功能描述:* |
| XC4003E-4PC84C | 功能描述:IC FPGA 100 CLB'S 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC4003E-4PC84I | 功能描述:IC FPGA I-TEMP 5V 4-SPD 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
发布紧急采购，3分钟左右您将得到回复。