参数资料
型号: XC4005E-4PQG160I
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 196 CLBS, 3000 GATES, 111 MHz, PQFP160
封装: PLASTIC, QFP-160
文件页数: 8/17页
文件大小: 75K
代理商: XC4005E-4PQG160I
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-116
February 11, 2000 (Version 1.8)
IOB Output Switching Characteristics Guidelines (Continued)
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Setup and Hold
Output (O) to clock (OK)
setup time
Output (O) to clock (OK)
hold time
Clock Enable (EC) to
clock (OK) setup
Clock Enable (EC) to
clock (OK) hold
TOOK
TOKO
TECOK
TOKEC
5.0
0
4.8
1.2
4.6
0
3.5
1.2
3.8
0
2.7
0.5
2.3
0
2.0
0
ns
Clock
Clock High
Clock Low
TCH
TCL
4.5
4.0
3.0
ns
Global Set/Reset (Note 3)
Delay from GSR net to Pad
GSR width
GSR inactive to first active
clock (OK) edge
TRPO
TMRW
TMRO
13.0
15.0
11.5
11.8
11.5
8.7
7.0
ns
Note 1:
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2:
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal
pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.
Note 3:
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
相关PDF资料
PDF描述
XC4005E-1PQG208C FPGA, 196 CLBS, 3000 GATES, 166 MHz, PQFP208
XC4005E-2PQG208C FPGA, 196 CLBS, 3000 GATES, 125 MHz, PQFP208
XC4005E-2PQG208I FPGA, 196 CLBS, 3000 GATES, 125 MHz, PQFP208
XC4005E-3PQG208C FPGA, 196 CLBS, 3000 GATES, 125 MHz, PQFP208
XC4005E-3PQG208I FPGA, 196 CLBS, 3000 GATES, 125 MHz, PQFP208
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