参数资料
型号: XC4006E-1TQ144C
厂商: Xilinx Inc
文件页数: 60/68页
文件大小: 0K
描述: IC FPGA C-TEMP 5V 1SPD 144-TQFP
产品变化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
标准包装: 60
系列: XC4000E/X
LAB/CLB数: 256
逻辑元件/单元数: 608
RAM 位总计: 8192
输入/输出数: 113
门数: 6000
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
R
May 14, 1999 (Version 1.6)
6-67
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6
D7
D0
D1
D2
1
TCA
2
TDC
4
TWTRB
3
TCD
6
TBUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA
Read Status
X6097
7
4
Description
Symbol
Min
Max
Units
Write
Effective Write time
(CS0, WS=Low; RS, CS1=High)
1TCA
100
ns
DIN setup time
2
TDC
60
ns
DIN hold time
3
TCD
0ns
RDY
RDY/BUSY delay after end of
Write or Read
4TWTRB
60
ns
RDY/BUSY active after beginning
of Read
760
ns
RDY/BUSY Low output (Note 4)
6
TBUSY
2
9
CCLK
periods
Notes:
1. Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS.RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Product Obsolete or Under Obsolescence
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