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参数资料
| 型号： | XC4013E-2BGG225C |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PBGA225 |
| 文件页数： | 14/17页 |
| 文件大小： | 75K |
| 代理商： | XC4013E-2BGG225C |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-106
February 11, 2000 (Version 1.8)
XC4000E CLB Characteristics Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted
CLB Switching Characteristics Guidelines
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via SR through H to X/Y outputs
C inputs via H to X/Y outputs
C inputs via DIN through H to X/Y outputs
TILO
TIHO
THH0O
THH1O
THH2O
2.7
4.7
4.1
3.7
4.5
2.0
4.3
3.3
3.6
1.6
2.7
2.4
2.2
2.6
1.3
2.2
1.9
1.6
1.9
ns
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to
X/Y outputs
CIN to COUT, bypass function generators
TOPCY
TASCY
TINCY
TSUM
TBYP
3.2
5.5
1.7
3.8
1.0
2.6
4.4
1.7
3.3
0.7
2.1
3.7
1.4
2.6
0.6
1.7
2.5
1.2
1.8
0.5
ns
Sequential Delays
Clock K to outputs Q
TCKO
3.7
2.8
1.9
ns
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
4.0
6.1
4.5
5.0
4.8
3.0
4.0
4.2
2.5
4.2
3.0
4.6
3.6
4.1
3.8
2.4
3.0
4.0
2.1
3.5
2.4
3.9
3.5
3.3
3.7
2.0
2.6
4.0
1.8
2.8
2.4
2.1
2.5
1.0
2.0
1.5
ns
相关PDF资料 |
PDF描述 |
|---|---|
| XC4013E-2BGG225I | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PBGA225 |
| XC4013E-3HQG240C | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| XC4013E-3HQG240I | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| XC4013E-4HQG240C | FPGA, 576 CLBS, 10000 GATES, 111 MHz, PQFP240 |
| XC4013E-4HQG240I | FPGA, 576 CLBS, 10000 GATES, 111 MHz, PQFP240 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4013E-2CB240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2CB240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2CB240M | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
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