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参数资料
| 型号： | XC4013E-4HQG208C |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, PQFP208 |
| 文件页数： | 6/17页 |
| 文件大小： | 75K |
| 代理商： | XC4013E-4HQG208C |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-114
February 11, 2000 (Version 1.8)
XC4000E IOB Input Switching Characteristic Guidelines (Continued)
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Device
Min
Max
Min
Max
Min
Max
Min
Max
Setup Times (TTL Inputs)
Pad to Clock (IK),
no delay
with delay
TPICK
TPICKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
10.9
11.1
11.3
11.8
14.0
2.6
8.2
8.7
9.2
9.6
9.8
10.2
11.4
2.0
6.0
6.1
6.2
6.3
6.4
7.9
9.4
10.0
1.5
4.8
5.1
5.8
6.0
7.6
8.2
–
ns
Setup Time (CMOS Inputs)
Pad to Clock (IK), no delay
with delay
TPICKC
TPICKDC
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
6.0
12.0
12.3
12.8
13.0
13.5
16.0
3.3
8.8
9.7
9.9
10.3
10.5
10.9
12.1
2.4
6.9
8.0
8.1
8.2
8.3
10.0
12.1
2.4
5.3
5.6
6.3
6.5
7.9
8.1
–
ns
(TTL or CMOS)
Clock Enable (EC) to Clock
(IK), no delay
with delay
TECIK
TECIKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.5
10.4
10.7
11.1
14.0
2.5
8.1
8.5
9.1
9.5
9.7
10.1
11.3
2.1
4.3
5.6
6.7
6.9
7.1
9.0
10.6
11.0
1.5
4.3
5.0
6.0
6.5
8.0
9.0
–
ns
Global Set/Reset (Note 3)
Delay from GSR net
through Q to I1, I2
GSR width
GSR inactive to first active
Clock (IK) edge
TRRI
TMRW
TMRI
13.0
12.0
11.5
7.8
11.5
6.8
10.0
6.8
ns
Note 1:
Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2:
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal
pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.
Note 3:
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
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