参数资料
| 型号： | XC4025E-3PG223C |
| 厂商： | Xilinx Inc |
| 文件页数： | 42/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA C-TEMP 5V 3SPD 223-CPGA |
| 产品变化通告： | XC4000(E,L) Discontinuation 01/April/2002 |
| 标准包装： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 1024 |
| 逻辑元件/单元数： | 2432 |
| RAM 位总计： | 32768 |
| 输入/输出数： | 192 |
| 门数： | 25000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 223-BCBGA |
| 供应商设备封装： | 223-CPGA（47.25x47.25） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页当前第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
May 14, 1999 (Version 1.6)
6-51
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Low. During this time delay, or as long as the PROGRAM
input is asserted, the conguration logic is held in a Cong-
uration Memory Clear state. The conguration-memory
frames are consecutively initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the congura-
tion frames and then tests the INIT input.
Initialization
During initialization and conguration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the nal initializa-
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250
s (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac-
tive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to deter-
mine the conguration mode. The appropriate interface
lines become active and the conguration preamble and
data can be loaded.Conguration
The 0010 preamble code indicates that the following 24 bits
represent the length count. The length count is the total
number of conguration clocks needed to load the com-
plete conguration data. (Four additional conguration
clocks are required to complete the conguration process,
as discussed below.) After the preamble and the length
count have been passed through to all devices in the daisy
chain, DOUT is held High to prevent frame start bits from
reaching any daisy-chained devices.
A specic conguration bit, early in the rst frame of a mas-
ter device, controls the conguration-clock rate and can
increase it by a factor of eight. Therefore, if a fast congu-
ration clock is selected by the bitstream, the slower clock
rate is used until this conguration bit is detected.
Each frame has a start eld followed by the frame-congu-
ration data bits and a frame error eld. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all congura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
Delaying Conguration After Power-Up
There are two methods of delaying conguration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 46 on page 50.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly dened. As long as PRO-
GRAM is Low, the FPGA keeps clearing its conguration
memory. When PROGRAM goes High, the conguration
memory is cleared one more time, followed by the begin-
ning of conguration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of conguration causes the
FPGA to wait after completing the conguration memory
clear operation. When INIT is no longer held Low exter-
nally, the device determines its conguration mode by cap-
turing its mode pins, and is ready to start the conguration
process. A master device waits up to an additional 250
s
to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
Start-Up
Start-up is the transition from the conguration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial conguration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that the
user-logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the conguration sig-
nals, and that the internal ip-ops are released from the
global Reset or Set at the right time.
Figure 47 describes start-up timing for the three Xilinx fam-
ilies in detail. The conguration modes can use any of the
four timing sequences.
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a xed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some exibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional exibility. The three
events — DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of soft-
ware options in the bitstream generation software.
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| XC4025E-3HQ304I | IC FPGA I-TEMP 5V 3SPD 304-HQFP |
| FMC36DRAH-S734 | CONN EDGECARD 72POS .100 R/A SLD |
| IDT70V07L35PF8 | IC SRAM 256KBIT 35NS 80TQFP |
| FMC28DRES-S93 | CONN EDGECARD 56POS .100 EYELET |
| IDT70V07L25PF8 | IC SRAM 256KBIT 25NS 80TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4025E-3PG223I | 功能描述:IC FPGA I-TEMP 5V 3SPD 223-CPGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4025E-3PG299C | 功能描述:IC FPGA C-TEMP 5V 3SPD 299-CPGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4025E-3PG299I | 功能描述:IC FPGA I-TEMP 5V 3SPD 299-CPGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4025E-4CB228B | 制造商:Xilinx 功能描述: |
| XC4025E-4HQ240C | 功能描述:IC FPGA C-TEMP 5V 4 SPD 240-HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
发布紧急采购，3分钟左右您将得到回复。