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参数资料
型号： XC4025E-4PG299C
厂商： Xilinx Inc
文件页数： 52/68页
文件大小： 0K
描述： IC FPGA C-TEMP 5V 4 SPD 299-CPGA
产品变化通告： XC4000(E,L) Discontinuation 01/April/2002
标准包装： 10
系列： XC4000E/X
LAB/CLB数： 1024
逻辑元件/单元数： 2432
RAM 位总计： 32768
输入/输出数： 256
门数： 25000
电源电压： 4.75 V ~ 5.25 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 299-BCBGA
供应商设备封装： 299-CPGA（52.3x52.3）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-60
May 14, 1999 (Version 1.6)
Conguration Timing
The seven conguration modes are discussed in detail in
this section. Timing specications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial conguration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 51 shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during conguration.
Figure 52: Slave Serial Mode Programming Switching Characteristics
XC4000E/X
MASTER
SERIAL
XC4000E/X,
XC5200
SLAVE
XC3100A
SLAVE
XC1700D
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2
M0 M1
DOUT
CCLK
CLK
VCC
+5 V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
DONE
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
M2
M0 M1
M1
PWRDN
M0
M2
(Low Reset Option Used)
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
VCC
X9025
N/C
Figure 51: Master/Slave Serial Mode Circuit Diagram
4 TCCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 TCCO
5 TCCL
2 TCCD
1 TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
Max
Units
CCLK
DIN setup
1
TDCC
20
ns
DIN hold
2
TCCD
0ns
DIN to DOUT
3
TCCO
30
ns
High time
4
TCCH
45
ns
Low time
5
TCCL
45
ns
Frequency
FCC
10
MHz
Note: Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Product Obsolete or Under Obsolescence
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XC4028EX-2HQ240C 制造商:Xilinx 功能描述:
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XC4028EX-3HQ208I 制造商:Xilinx 功能描述:
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