参数资料
| 型号： | XC4044XL-3HQ240I |
| 厂商： | Xilinx Inc |
| 文件页数： | 20/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 3SPD 240HQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 1600 |
| 逻辑元件/单元数： | 3800 |
| RAM 位总计： | 51200 |
| 输入/输出数： | 193 |
| 门数： | 44000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP 裸露焊盘 |
| 供应商设备封装： | 240-PQFP（32x32） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
May 14, 1999 (Version 1.6)
6-31
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices stag-
gered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 28).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing exibility. Double-length lines are connected by way
of the programmable switch matrices. Routing connectivity
is shown in Figure 27.
Quad Lines (XC4000X only)
XC4000X devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as dia-
monds in Figure 27 on page 30). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices stag-
gered, so that each line goes through a buffered switch
matrix at every fourth CLB location in that row or column.
(See Figure 29.)
The buffered switch matrixes have four pins, one on each
edge. All of the pins are bidirectional. Any pin can drive any
or all of the other pins.
Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 26, with the addition of a program-
mable buffer. There can be up to two independent inputs
and up to two independent outputs. Only one of the inde-
pendent inputs can be buffered.
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded signal
is typically buffered, while a lightly loaded one is not. One
scenario is to alternate buffers and pass transistors. This
allows both vertical and horizontal quad lines to be buffered
at alternating buffered switch matrices.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000X
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high
fan-out nets.
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore imple-
ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See “Three-State Buffers” on
page 26 for more details.)
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000X) pull-up resistors. To acti-
vate these resistors, attach a PULLUP symbol to the
long-line net. The software automatically activates the
appropriate number of pull-ups. There is also a weak
keeper at each end of these two horizontal longlines. This
CLB
PSM
CLB
Doubles
Singles
Doubles
X6601
Figure 28: Single- and Double-Length Lines, with
Programmable Switch Matrices (PSMs)
CLB
X9014
Figure 29: Quad Lines (XC4000X only)
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| 65801-117LF | CLINCHER RECEPTACLE ASSY TIN |
| XC4044XL-3HQ240C | IC FPGA C-TEMP 3.3V 3SPD 240HQFP |
| XC4044XL-3HQ208I | IC FPGA I-TEMP 3.3V 3SPD 208HQFP |
| 65801-021LF | CLINCHER RECEPTACLE ASS'-Y-TIN |
| FMC19DRES | CONN EDGECARD 38POS .100 EYELET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4044XL-3HQ304C | 功能描述:IC FPGA C-TEMP 3.3V 3SPD 304HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4044XL-3HQ304I | 功能描述:IC FPGA I-TEMP 3.3V 3SPD 304HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4044XLA-07BG352C | 制造商:Xilinx 功能描述: |
| XC4044XLA-07HQ208C | 制造商:Xilinx 功能描述: |
| XC4044XLA-07HQ304C | 制造商:Xilinx 功能描述: |
发布紧急采购，3分钟左右您将得到回复。