参数资料
| 型号： | XC4052XL-2BG560I |
| 厂商： | Xilinx Inc |
| 文件页数： | 68/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 2SPD 560MBGA |
| 产品变化通告： | XC4000(XL,XLA,E) Discontinuation 15/Nov/2004 |
| 标准包装： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 1936 |
| 逻辑元件/单元数： | 4598 |
| RAM 位总计： | 61952 |
| 输入/输出数： | 352 |
| 门数： | 52000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 560-LBGA，金属 |
| 供应商设备封装： | 560-MBGA（42.5x42.5） |
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R
May 14, 1999 (Version 1.6)
6-13
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
tions of the CLB, with the exception of the redenition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D ip-ops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered
(synchronous)
RAM
simplies
timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
nals. An internal write pulse is generated that performs the
CLB congured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
The Write Clock input (WCLK) can be congured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB ip-ops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are congured
as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
gured as edge-triggered RAM.
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Figure 3:
Edge-Triggered RAM Write Timing
Table 5: Single-Port Edge-Triggered RAM Signals
RAM Signal
CLB Pin
Function
D
D0 or D1 (16x2,
16x1), D0 (32x1)
Data In
A[3:0]
F1-F4 or G1-G4
Address
A[4]
D1 (32x1)
Address
WE
Write Enable
WCLK
K
Clock
SPO
(Data Out)
F’ or G’
Single Port Out
(Data Out)
Product Obsolete or Under Obsolescence
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