参数资料
型号: XC5210-4PQ100C
厂商: Xilinx, Inc.
英文描述: Field Programmable Gate Arrays
中文描述: 现场可编程门阵列
文件页数: 44/73页
文件大小: 598K
代理商: XC5210-4PQ100C
R
November 5, 1998 (Version 5.2)
7-131
XC5200 Series Field Programmable Gate Arrays
7
XC5200 IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
T
PI
5.7
5.0
4.8
3.3
Pad to I (with delay)
T
PID
11.4
10.2
9.5
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast)
T
OPF
4.6
4.5
3.5
Output (O) to Pad (slew-limited)
T
OPS
9.5
8.4
8.0
5.0
From clock (CK) to output pad (fast), using direct connect between Q
and output (O)
T
OKPOF
10.1
9.3
8.3
7.5
From clock (CK) to output pad (slew-limited), using direct connect be-
tween Q and output (O)
T
OKPOS
14.9
13.1
11.8
10.0
3-state to Pad active (fast)
T
TSONF
5.6
5.2
4.9
4.6
3-state to Pad active (slew-limited)
T
TSONS
10.4
9.0
8.3
6.0
Internal GTS to Pad active
T
GTS
17.7
15.9
14.7
13.5
Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times.
2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
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