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型号： XC5VFX70T-1FF665CES
厂商： Xilinx Inc
文件页数： 88/91页
文件大小： 0K
描述： IC FPGA VIRTEX5FX 70K 665FCBGA
标准包装： 1
系列： Virtex®-5 FXT
LAB/CLB数： 5600
逻辑元件/单元数： 71680
RAM 位总计： 5455872
输入/输出数： 360
电源电压： 0.95 V ~ 1.05 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 665-BBGA，FCBGA
供应商设备封装： 665-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
DK-V5-EMBD-ML507-G-J-ND - DEV KIT V5 W/ISM & EDK JAPAN
DK-V5-EMBD-ML507-G-ND - DEV KIT V5 W/ISM & EDK
HW-V5-ML507-UNI-G-ND - EVAL PLATFORM V5 FXT
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
89
06/26/07
3.3
Added conditions to DVPPIN in Table 28, page 14.
Changed the FGTXMAX symbol name to FGTPMAX.
Updated GTP maximum line rates to 3.75 Gb/s in Table 30, page 16.
Updated maximum frequencies in Table33, page17.
Added 3.75 Gb/s condition and changed maximum value of FGTX in Table 34, page 17.
Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of FGRX in Table 35,
page 18.
Changed analog input common mode ranges in Table 51, page 26.
Changed TPKGSKEW values in Table99, page84.
07/26/07
3.4
Added maximum value of IREF to Table 3, page 2.
Revised Table 54 and changed the design software version in Table 55 for production devices.
In Table 64, page 44, added High Performance Mode to Note 2.
In Table 70, page 51, revised description of TSMDCCK/TSMCCKD.
Added Note 4 to TDUTYCYCRANGE_200_400 frequency range in Table 78, page 59.
In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 96.
09/27/07
3.5
Added IBATT value and Note 2 to Table 3.
Added DRP Clock Frequency and Note 4 to Table 51. Revised the typical and maximum values and
units for gain error and bipolar gain error.
Removed unsupported XC5VSX95T -3 speed grade from Table 54 and Table 55.
Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from Table 51. Also
updated LVDSEXT, 2.5V in Table 59.
Added values to Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK in
Table 70.
In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 97.
11/05/07
3.6
Removed note 1 from Table 52, page 28. FMAX of clock is not an applicable limitation.
Revised DDR2 memory interface performance in Table53, page29.
Revised Table 55 to add ISE 9.2i SP3 where applicable.
Removed XC5VSX95T -3 speed grade support from applicable tables.
Removed unsupported I/O standard (LVPECL_33) from Table 58 and added LVPECL_25.
Added TSMCO and TSMCKBY to Table 70, page 51.
Revised note 3 in Table 76, page 57 and Table77, page58.
Clarified notes in Table 87 to Table 90, and Table 94 to Table 97.
Revised note 1 in Table 99.
12/11/07
3.7
Added new devices (XC5VLX20T, XC5VLX155, and XC5VLX155T) throughout document.
Removed -3 speed grade from XC5VSX95T device lists.
Added Table 31, page 16.
Revised Virtex-5 Device Pin-to-Pin Output Parameter Guidelines in Table 87 through Table 90, and
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines in Table 90 and Table 92 through Table 97. Also
revised Note 1 on Table 92 through Table 97.
Revised Note 1 on Table 99.
02/05/08
3.8
Updated date on version 3.7. Other minor typographical edits.
Updated the sentence: Xilinx does not specify the current or I/O behavior for other power-on sequences,
on page 6.
Added values and notes to Table 27, page 14. Removed ICCINTQ since it is included in Table 4, page 3.
Combined IVTTRXCQ into IVTTRXQ values.
Revised TLLSKEW values in Table 34, page 17.
Revised RXPPMTOL values and note 1 in Table 35, page 18.
Revised -2 performance value for SPI-4.2 in Table 53, page 29.
Added TIODDO_T, TIODDO_IDATAIN, TIODDO_ODATAIN, and Note 3 to Table 64, page 44.
Split out the FMAX rows in Table 71 and the FOUTMAX rows in Table 74, revised -2 value for smallest
devices in both tables.
Added Table 75: PLL in PMCD Mode Switching Characteristics, page 56.
Updated Table 4 and Table 84 to Table 98 to match speed grade designations listed in Table 54.
Revised Note 1 on Table 96 and Table 97.
Date
Version
Revision
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XC5VFX70T-1FF665I 功能描述:IC FPGA VIRTEX-5FXT 665FFBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-5 FXT 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VFX70T-1FFG1136C 功能描述:IC FPGA VIRTEX-5FX 70K 1136-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-5 FXT 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VFX70T-1FFG1136CES 功能描述:IC FPGAVIRTEX5FX ES 70K 1136FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-5 FXT 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789
XC5VFX70T-1FFG1136I 功能描述:IC FPGA VIRTEX-5FX 70K 1136-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-5 FXT 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VFX70T-1FFG665C 功能描述:IC FPGA VIRTEX-5FX 70K 665-FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-5 FXT 标准包装:24 系列:ECP2 LAB/CLB数:1500 逻辑元件/单元数:12000 RAM 位总计:226304 输入/输出数:131 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28）
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