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型号： XC5VLX110-1FF676I
厂商： Xilinx Inc
文件页数： 67/91页
文件大小： 0K
描述： IC FPGA VIRTEX-5 110K 676FBGA
标准包装： 1
系列： Virtex®-5 LX
LAB/CLB数： 8640
逻辑元件/单元数： 110592
RAM 位总计： 4718592
输入/输出数： 440
电源电压： 0.95 V ~ 1.05 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 676-BBGA，FCBGA
供应商设备封装： 676-FCBGA（27x27）
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF676-500-G-ND - BOARD DEV VIRTEX 5 FF676
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
7
SelectIO DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL
–0.3
0.8
2.0
3.45
0.4
2.4
Note(3)
LVCMOS33,
LVDCI33
–0.3
0.8
2.0
3.45
0.4
VCCO – 0.4
Note(3)
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
VCCO +0.3
0.4
VCCO – 0.4
Note(3)
LVCMOS18,
LVDCI18
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
0.45
VCCO – 0.45
Note(4)
LVCMOS15,
LVDCI15
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note(4)
LVCMOS12
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note(6)
PCI33_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
PCI66_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
PCI-X(5)
–0.2
35% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
GTLP
–0.3
VREF –0.1
VREF + 0.1
–
0.6
N/A
36
N/A
GTL
–0.3
VREF –0.05
VREF +0.05
–
0.4
N/A
32
N/A
HSTL I_12
–0.3
VREF –0.1
VREF +0.1
VCCO + 0.3
25% VCCO
75% VCCO
6.3
HSTL I(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
8
–8
HSTL II(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
16
–16
HSTL III(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
24
–8
HSTL IV(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
48
–8
DIFF HSTL I(2)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
DIFF HSTL II(2)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
SSTL2 I
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3
VTT –0.61
VTT + 0.61
8.1
–8.1
SSTL2 II
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3
VTT –0.81
VTT + 0.81
16.2
–16.2
DIFF SSTL2 I
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
–
DIFF SSTL2 II
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
–
SSTL18 I
–0.3
VREF – 0.125
VREF + 0.125
VCCO +0.3
VTT –0.47
VTT + 0.47
6.7
–6.7
SSTL18 II
–0.3
VREF – 0.125
VREF +0.125
VCCO +0.3
VTT –0.60
VTT + 0.60
13.4
–13.4
DIFF SSTL18 I
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
–
DIFF SSTL18 II
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
–
Notes:
1.
Tested according to relevant specifications.
2.
Applies to both 1.5V and 1.8V HSTL.
3.
Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4.
Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5.
For more information on PCI33_3, PCI66_3, and PCI-X, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
6.
Supported drive strengths of 2, 4, 6, or 8 mA.
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