参数资料
型号: XC5VLX30-1FFG324I
厂商: Xilinx Inc
文件页数: 79/91页
文件大小: 0K
描述: IC FPGA VIRTEX-5 30K 324FBGA
标准包装: 1
系列: Virtex®-5 LX
LAB/CLB数: 2400
逻辑元件/单元数: 30720
RAM 位总计: 1179648
输入/输出数: 220
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 324-BBGA,FCBGA
供应商设备封装: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
80
TPSDCMPLL/
TPHDCMPLL
No Delay Global Clock and IFF(2) with
DCM and PLL in System-Synchronous Mode
XC5VTX150T
N/A
2.00
–0.41
2.22
–0.41
ns
XC5VTX240T
N/A
2.25
–0.40
2.51
–0.40
ns
XC5VFX30T
1.97
–0.36
2.08
–0.36
2.21
–0.36
ns
XC5VFX70T
1.92
–0.44
2.03
–0.44
2.16
–0.44
ns
XC5VFX100T
2.40
–0.59
2.51
–0.59
2.66
–0.58
ns
XC5VFX130T
2.46
–0.51
2.64
–0.51
2.89
–0.51
ns
XC5VFX200T
N/A
2.44
–0.31
2.59
–0.30
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 96: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
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