参数资料
型号: XC5VLX50T-2FFG665C
厂商: Xilinx Inc
文件页数: 74/91页
文件大小: 0K
描述: IC FPGA VIRTEX-5 50K 665FCBGA
产品变化通告: Step Intro and Pkg Change 11/March/2008
标准包装: 1
系列: Virtex®-5 LXT
LAB/CLB数: 3600
逻辑元件/单元数: 46080
RAM 位总计: 2211840
输入/输出数: 360
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 665-BBGA,FCBGA
供应商设备封装: 665-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
76
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VTX150T
N/A
1.82
–0.56
1.95
–0.56
ns
XC5VTX240T
N/A
2.05
–0.43
2.26
–0.43
ns
XC5VFX30T
1.82
–0.40
1.93
–0.40
2.09
–0.40
ns
XC5VFX70T
1.79
–0.30
1.90
–0.30
2.07
–0.30
ns
XC5VFX100T
1.81
–0.43
1.91
–0.40
2.09
–0.38
ns
XC5VFX130T
1.79
–0.29
1.95
–0.28
2.14
–0.24
ns
XC5VFX200T
N/A
2.06
–0.14
2.29
–0.14
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
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