参数资料
型号: XC5VTX240T-1FF1759I
厂商: Xilinx Inc
文件页数: 89/91页
文件大小: 0K
描述: IC FPGA VIRTEX5TXT 240K 1759FBGA
标准包装: 1
系列: Virtex®-5 TXT
LAB/CLB数: 18720
逻辑元件/单元数: 239616
RAM 位总计: 11943936
输入/输出数: 680
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 1759-BBGA,FCBGA
供应商设备封装: 1759-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
9
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100
Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL
, see UG190:
Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources.
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information.
Table 11: LVPECL DC Specifications
Symbol
DC Parameter
Min
Typ
Max
Units
VOH
Output High Voltage
VCC – 1.025
1.545
VCC –0.88
V
VOL
Output Low Voltage
VCC – 1.81
0.795
VCC –1.62
V
VICM
Input Common-Mode Voltage
0.6
2.2
V
VIDIFF
Differential Input Voltage(1,2)
0.100
1.5
V
Notes:
1.
Recommended input maximum voltage not to exceed VCCO +0.2V.
2.
Recommended input minimum voltage not to go below –0.5V.
Table 12: Processor Block Switching Characteristics
Clock Name
Description
Speed Grade
Units
-3
-2
-1
CPMC440CLK
CPU clock
550
475
400
MHz
CPMINTERCONNECTCLK
Xbar clock
366.6
316.6
266.6
MHz
CPMPPCS0PLBCLK
Slave 0 PLB clock(1)
183.3
158.3
133.3
MHz
CPMPPCS1PLBCLK
Slave 1 PLB clock(1)
183.3
158.3
133.3
MHz
CPMPPCMPLBCLK
Master PLB clock(1)
183.3
158.3
133.3
MHz
CPMMCCLK
Memory interface clock(1)(2)
366.6
316.6
266.6
MHz
CPMFCMCLK
FCM clock(1)
275
237.5
200
MHz
CPMDCRCLK
FPGA logic DCR clock(1)
183.3
158.3
133.3
MHz
CPMDMA0LLCLK
DMA0 LL clock(1)
250
200
MHz
CPMDMA1LLCLK
DMA1 LL clock(1)
250
200
MHz
CPMDMA2LLCLK
DMA2 LL clock(1)
250
200
MHz
CPMDMA3LLCLK
DMA3 LL clock(1)
250
200
MHz
JTGC440TCK
JTAG clock
50
MHz
CPMC440TIMERCLOCK
Timer clock
275
237.5
200
MHz
Notes:
1.
Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent.
2.
Refer to DS567 for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC 440 Processors.
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