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| 型号： | XC6108C16AMR-G |
| 厂商： | Torex Semiconductor Ltd |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR 1.6V SOT25-5 |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 电压 - 阀值： | 1.6V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-25 |
| 包装： | 带卷 (TR) |
XC6108 Series
■ OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on page 14.
① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
to the power supply input voltage, (V IN : 1.0V MIN., 6.0V MAX.). While the sense pin voltage (V SE N ) starts dropping to
reach the detect voltage (V DF ) (V SEN >V DF ), the output voltage (V OUT ) keeps the “High” level (=V IN ).
* If a pull-up resistor of the XC6108N series (N-ch open drain) is connected to added power supply different from the input
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (V SEN =V DF ), an N-ch transistor
(M1) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An
inverter (Inv . 1) operates as a comparator of the reference voltage V IN , and the output voltage changes into the “Low” level
(=V SS ). The detect delay time [t DF ] is defined as time which ranges from V SEN =V DF to the V OUT of “Low” level
(especially, when the Cd pin is not connected: t DF0 ).
③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground
voltage (=V SS ) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to
reach the release voltage (V SEN < V DF +V HYS ).
④ When the sense pin voltage continues to increase up to the release voltage level (V DF +V HYS ), the N-ch transistor (M1) for
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay). The inverter (Inv . 1) will operate as a comparator (Rise Logic Threshold: V TLH =V TCD , Fall Logic
Threshold: V THL =V SS ) while the sense pin voltage keeps higher than the detect voltage (V SEN > V DF ).
⑤ While the delay capacitance pin voltage (V CD ) rises to reach the delay capacitance pin threshold voltage (V TCD ) with the
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC
series circuit. Assuming the time to the release delay time (t DR ), it can be given by the formula (1).
t DR = － Rdelay × Cd × In (1 － V TCD / V IN ) … (1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0M Ω (TYP.) and
the delay capacitance pin voltage is V IN /2 (TYP.)
t DR = Rdelay × Cd × 0.69 … (2)
＊： Rdelay is 2.0M Ω（ TYP. ）
As an example, presuming that the delay capacitance is 0.68 μ F, t DR is :
2.0 × 10 6 × 0.68 × 10 -6 × 0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the
ground (=V SS ) level because time described in ③ is short.
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (V CD =V TCD ), the inverter
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=V IN ) level. t DR0 is defined as time
which ranges from V SEN =V DF +V HYS to the V OUT of “High” level without connecting to the Cd.
⑦ While the sense voltage is higher than the detect voltage (V SEN > V DF ), the delay capacitance pin is charged until the
delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=V IN )
level.
12/22
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