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参数资料
| 型号： | XC6601B151MR-G |
| 厂商： | Torex Semiconductor Ltd |
| 文件页数： | 13/33页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.5V .4A SOT25-5 |
| 标准包装： | 3,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.5V |
| 输入电压： | 最高 3 V |
| 电压 - 压降（标准）： | 0.129V @ 400mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 400mA（最小） |
| 电流 - 限制（最小）： | 400mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-25 |
| 包装： | 带卷 (TR) |
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XC6601
Series
■ OPERATIONAL EXPLANATION (Continued)
<Under Voltage Lock Out (UVLO) >
When the V BIAS pin voltage drops below 2.0V (TYP.) or V IN pin voltage drops below 0.4V (TYP.), the output driver transistor is
forced OFF by UVLO function to prevent false output caused by unstable operation of the internal circuitry. When the V BIAS pin
voltage rise at 2.2V (TYP.) or the V IN pin voltage rises at 0.4V (TYP.), the UVLO function is released. The driver transistor is
turned in the ON state and start to operate voltage regulation.
<CE Pin>
The IC internal circuitry can be shutdown via the signal from the CE pin with the XC6601 series. In shutdown mode, output at the
V OUT pin will be pulled down to the V SS level via R1 & R2. However, as for the XC6601 series, the CL auto-discharge resistor is
connected in parallel to R1 and R2 while the power supply is applied to the V IN pin. Therefore, time until the V OUT pin reaches the
V SS level becomes short.
The CE pin of XC6601A has pull-down circuitry so that CE input current increase during IC operation. The CE pin of XC6601B
does not have pull-down circuitry so that logic is not fixed when the CE pin is open. If the CE pin voltage is taken from V BIAS pin
or V SS pin then logic is fixed and the IC will operate normally. However, supply current may increase as a result of through current
in the IC's internal circuitry when medium voltage is input.
■ NOTE ON USE
1.
2.
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5.
6.
Please use this IC within the stated absolute maximum ratings. The IC is liable to malfunction should the ratings be
exceeded.
Where wiring impedance is high, operations may become unstable due to noise and/or phase lag depending on output
current. Please keep the resistance low between V BIAS and V SS wiring or V IN and V SS wiring in particular.
Please wire the bias capacitor (C BIAS ), input capacitor (C IN ) and the output capacitor (C L ) as close to the IC as possible.
Capacitance values of these capacitors (C BIAS, C IN, C L ) are decreased by the influences of bias voltage and ambient
temperature. Care shall be taken for capacitor selection to ensure stability of phase compensation from the point of ESR
influence.
In case of the output capacitor more than C L =22 μ F is used, ringing of input current occurs when rising time.
V IN and CE should be applied at least 10 μ s after the bias voltage V BIAS reaches the requested voltage.
If V IN and CE
are applied within 10 μ s, inrush current like 1A may occurs.
13/33
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