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型号： XC6SLX150T-2FG676I
厂商： Xilinx Inc
文件页数： 2/89页
文件大小： 0K
描述： IC FPGA SPARTAN 6 676FGGBGA
标准包装： 40
系列： Spartan® 6 LXT
LAB/CLB数： 11519
逻辑元件/单元数： 147443
RAM 位总计： 4939776
输入/输出数： 396
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 676-BGA
供应商设备封装： 676-FBGA（27x27）
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
www.xilinx.com
Product Specification
10
In Table 9 and Table 10, values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over
the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are
chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the
respective VOL and VOH voltage levels shown. Other standards are sample tested.
Table 9: Single-Ended I/O Standard DC Input and Output Levels
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL
–0.5
0.8
2.0
4.1
0.4
2.4
Note 2
LVCMOS33
–0.5
0.8
2.0
4.1
0.4
VCCO –0.4
Note 2
LVCMOS25
–0.5
0.7
1.7
4.1
0.4
VCCO –0.4
Note 2
LVCMOS18
–0.5
0.38
0.8
4.1
0.45
VCCO –0.45
Note 2
LVCMOS18 (-1L)
–0.5
0.33
0.71
4.1
0.45
VCCO –0.45
Note 2
LVCMOS18_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
0.45
VCCO –0.45
Note 2
LVCMOS15
–0.5
0.38
0.8
4.1
25% VCCO
75% VCCO
Note 3
LVCMOS15 (-1L)
–0.5
0.33
0.71
4.1
25% VCCO
75% VCCO
Note 3
LVCMOS15_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
25% VCCO
75% VCCO
Note 3
LVCMOS12
–0.5
0.38
0.8
4.1
0.4
VCCO –0.4
Note 4
LVCMOS12 (-1L)
–0.5
0.33
0.71
4.1
0.4
VCCO –0.4
Note 4
LVCMOS12_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
0.4
VCCO –0.4
Note 4
PCI33_3
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
1.5
–0.5
PCI66_3
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
1.5
–0.5
I2C
–0.5
25% VCCO
70% VCCO
4.1
20% VCCO
–3
–
SMBUS
–0.5
0.8
2.1
4.1
0.4
–
4
–
SDIO
–0.5
12.5% VCCO
75% VCCO
4.1
12.5% VCCO
75% VCCO
0.1
–0.1
MOBILE_DDR
–0.5
20% VCCO
80% VCCO
4.1
10% VCCO
90% VCCO
0.1
–0.1
HSTL_I
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO –0.4
8
–8
HSTL_II
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
16
–16
HSTL_III
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
24
–8
HSTL_I_18
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
11
–11
HSTL_II_18
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
22
–22
HSTL_III_18
–0.5
VREF –0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
30
–11
SSTL3_I
–0.5
VREF –0.2
VREF +0.2
4.1
VTT –0.6
VTT +0.6
8
–8
SSTL3_II
–0.5
VREF –0.2
VREF +0.2
4.1
VTT –0.8
VTT + 0.8
16
–16
SSTL2_I
–0.5
VREF –0.15
VREF +0.15
4.1
VTT –0.61
VTT + 0.61
8.1
–8.1
SSTL2_II
–0.5
VREF –0.15
VREF +0.15
4.1
VTT –0.81
VTT + 0.81
16.2
–16.2
SSTL18_I
–0.5
VREF – 0.125
VREF + 0.125
4.1
VTT –0.47
VTT + 0.47
6.7
–6.7
SSTL18_II
–0.5
VREF – 0.125
VREF + 0.125
4.1
VTT –0.60
VTT + 0.60
13.4
–13.4
SSTL15_II
–0.5
VREF –0.1
VREF +0.1
4.1
VTT –0.4
VTT + 0.4
13.4
–13.4
Notes:
1.
Tested according to relevant specifications.
2.
Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
3.
Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
4.
Using drive strengths of 2, 4, 6, 8, or 12 mA.
5.
For more information, refer to UG381: Spartan-6 FPGA SelectIO Resources User Guide.
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