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参数资料
| 型号： | XC6VSX475T-L1FFG1759I |
| 厂商： | Xilinx Inc |
| 文件页数： | 10/11页 |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX 6 476K 1759FFGBGA |
| 产品培训模块： | Virtex-6 FPGA Overview |
| 产品变化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex® 6 SXT |
| LAB/CLB数： | 37200 |
| 逻辑元件/单元数： | 476160 |
| RAM 位总计： | 39223296 |
| 输入/输出数： | 840 |
| 电源电压： | 0.91 V ~ 0.97 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1759-BBGA，FCBGA |
| 供应商设备封装： | 1759-FCBGA |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
8
The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are
made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test
access port (TAP).
Low-Power Gigabit Transceivers
Ultra-fast serial data transmission between ICs, over the backplane, or over longer distances is becoming increasingly
popular and important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the
signal integrity issues at these high data rates.
All but one Virtex-6 device has between 8 to 72 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter
and receiver capable of operating at a data rate between 480 Mb/s and 6.6 Gb/s. Lower data rates can be achieved using
FPGA logic-based oversampling. Each GTH transceiver is a combined transmitter and receiver capable of operating at a
rate between 2.488 Gb/s and 11.18 Gb/s. The GTX transmitter and receiver are independent circuits that use separate
PLLs to multiply the reference frequency input by certain programmable numbers between 4 and 25, to become the bit-serial
data clock. The GTH transceiver is a purpose-built design for 10 Gb/s rates and shares a single high-performance PLL
between four transmitter and receiver circuits. Each GTX and GTH transceiver has a large number of user-definable features
and parameters. All of these can be defined during device configuration, and many can also be modified during operation.
Transmitter
The GTX transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, 20, 32, or 40. The
GTH transmitter offers bit widths of 16, 20, 32, 40, 64, or 80 to allow additional timing margin for high-performance designs.
These transmitter outputs drive the PC board with a single-channel differential current-mode logic (CML) output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B,
64B/66B, or the 64B/67B (GTX only) algorithm to guarantee a sufficient number of transitions. The bit-serial output signal
drives two package pins with complementary CML signals. This output signal pair has programmable signal swing as well as
programmable pre-emphasis to compensate for PC board losses and other interconnect characteristics.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel
stream of words, each 8, 10, 16, 20, 32, or 40 bits wide. The GTH transceiver offers 16, 20, 32, 40, 64, and 80 bit widths to
allow greater timing margin. The receiver takes the incoming differential data stream, feeds it through a programmable
equalizer (to compensate for PC board and other interconnect characteristics), and uses the FREF input to initiate clock
recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and
optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into
the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio for GTX transceivers can be 8, 10, 16, 20,
32, or 40. The serial-to-parallel conversion ratio for GTH transceivers can be 16, 20, 32, 40, 64, or 80 for GTH.
Out-of-Band Signaling
The GTX transceivers provide Out-of-Band (OOB) signaling, often used to send low-speed signals from the transmitter to
the receiver, while high-speed serial data transmission is not active, typically when the link is in a power-down state or has
not been initialized. This benefits PCI Express and SATA/SAS applications.
Integrated Interface Blocks for PCI Express Designs
The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission
uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.
The PCI Express Base Specification Revision 2.0 is backwards compatible with Revision 1.1 and defines a configurable raw
data rate of 2.5 Gb/s, or 5.0 Gb/s per lane in each direction. To scale bandwidth, the specification allows multiple lanes to be
joined to form a larger link between PCI Express devices.
All Virtex-6 devices (except the XC6VLX760) include at least one integrated interface block for PCI Express technology that
can be configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.0. The Root Port
can be used to build the basis for a compatible Root Complex, to allow custom FPGA-FPGA communication via the PCI
Express protocol, and to attach ASSP Endpoint devices such as Fibre Channel HBAs to the FPGA.
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