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参数资料
| 型号： | XC95144XL-10TQG144I |
| 厂商： | Xilinx Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 3.2K 144MCELL 144-TQFP |
| 标准包装： | 60 |
| 系列： | XC9500XL |
| 可编程类型： | 系统内可编程（最少 10,000 次编程/擦除循环） |
| 最大延迟时间 tpd(1)： | 10.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 8 |
| 宏单元数： | 144 |
| 门数： | 3200 |
| 输入/输出数： | 117 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | 122-1375 |
DS056 (v2.0) April 3, 2007
1
Product Specification
1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
-
100-pin TQFP (81 user I/O pins)
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144-pin TQFP (117 user I/O pins)
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144-CSP (117 user I/O pins)
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Pb-free available for all packages
Optimized for high-performance 3.3V systems
-
Low power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
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3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
Fast FLASH technology
Advanced system features
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In-system programmable
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Superior pin-locking and routability with
Fast CONNECT II switch matrix
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Extra wide 54-input Function Blocks
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Up to 90 product-terms per macrocell with
individual product-term allocation
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Local clock inversion with three global and one
product-term clocks
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Individual output enable per output pin with local
inversion
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Input hysteresis on all user and boundary-scan pin
inputs
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Bus-hold circuitry on all user pin inputs
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Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
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20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95144XL High Performance
CPLD
DS056 (v2.0) April 3, 2007
00
Product Specification
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相关代理商/技术参数 |
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| XC95144XL-5CS144C | 制造商:Xilinx 功能描述:CPLD XC9500XL 3.2K GATES 144 MCRCLLS 178.6MHZ 0.35UM 3.3V 14 - Trays |
| XC95144XL-5CSG144C | 功能描述:IC CPLD 144MCELL 5NS 144-CSBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:XC9500XL 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC95144XL5TQ100C | 制造商:Xilinx 功能描述: |
| XC95144XL-5TQ100C | 功能描述:IC CPLD 144 MCELL 3.3V 100-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:XC9500XL 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC95144XL-5TQ100C0696 | 制造商:Xilinx 功能描述: |
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