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参数资料
| 型号： | XC9572XV-5CS48C |
| 厂商： | Xilinx Inc |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 2.5V ISP 48-CSP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 416 |
| 系列： | XC9500XV |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 5.0ns |
| 电压电源 - 内部： | 2.37 V ~ 2.62 V |
| 逻辑元件/逻辑块数目： | 4 |
| 宏单元数： | 72 |
| 门数： | 1600 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-FBGA，CSPBGA |
| 供应商设备封装： | 48-CSBGA（7x7） |
| 包装： | 托盘 |
DS052 (v3.0) June 25, 2007
1
Product Specification
2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC9572XV devices with equivalent XC9572XL devices
in all designs as soon as possible. Recommended replace-
ments are pin compatible, however require a VCC change to
3.3V, and a recompile of the design file. In addition, there is
no 1.8V I/O support. See XCN07010 for details regarding
this
discontinuation,
including
device
replacement
recomendations for the XC9572XV CPLD.
Features
72 macrocells with 1,600 usable gates
Available in small footprint packages
-
44-pin VQFP (34 user I/O pins)
-
100-pin TQFP (72-user I/O pins)
Optimized for high-performance 2.5V systems
-
Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold ciruitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
20 year data retention
-
ESD protection exceeding 2,000V
Description
The XC9572XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
ICCINT (taken from simulation) is:
ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
where:
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
fMAX = max clocking frequency in the device
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP361, “Planning for High Speed
0
XC9572XV High-performance
CPLD
DS052 (v3.0) June 25, 2007
05
Product Specification
R
Product Obsolete/Under Obsolescence
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相关代理商/技术参数 |
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|---|---|
| XC9572XV-5CS48I | 制造商:XILINX 制造商全称:XILINX 功能描述:XC9572XV High-performance CPLD |
| XC9572XV-5PC44C | 功能描述:IC CPLD 2.5V ISP 44-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:XC9500XV 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC9572XV-5PC44I | 制造商:XILINX 制造商全称:XILINX 功能描述:XC9572XV High-performance CPLD |
| XC9572XV-5TQ100C | 功能描述:IC CPLD 2.5V ISP 100-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:XC9500XV 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC9572XV-5TQ100I | 制造商:XILINX 制造商全称:XILINX 功能描述:XC9572XV High-performance CPLD |
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