参数资料
| 型号： | XCS05XL-4VQG100C |
| 厂商： | Xilinx Inc |
| 文件页数： | 29/83页 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-XL FPGA 5K 100-VQFP |
| 产品变化通告： | Product Discontinuation 26/Oct/2011 |
| 标准包装： | 90 |
| 系列： | Spartan®-XL |
| LAB/CLB数： | 100 |
| 逻辑元件/单元数： | 238 |
| RAM 位总计： | 3200 |
| 输入/输出数： | 77 |
| 门数： | 5000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
| 其它名称： | 122-1289 |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
35
Product Specification
R
Product Obsolete/Under Obsolescence
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL family Express mode, the length count bits are
ignored, and DOUT is held Low, to disable the next device in
the pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL family Express mode, when the first device is
fully programmed, DOUT goes High to enable the next
device in the chain.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 30.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL FPGA
PROGRAM pin has a permanent weak pull-up.
Avoid holding PROGRAM Low for more than 500
μs. The
500
μs maximum limit is only a recommendation, not a
requirement. The only effect of holding PROGRAM Low for
more than 500
μs is an increase in current, measured at
about 40 mA in the XCS40XL. This increased current can-
not damage the device. This applies only during reconfigu-
ration, not during power-up. The INIT pin can also be held
Low to delay reconfiguration, and the same characteristics
apply as for the PROGRAM pin.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
Figure 30: Power-up Configuration Sequence
INIT
High? if
Master
Sample
Mode Line
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
VCC
Valid
No
Yes
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3
μs per Frame
Master Delays Before
Sampling Mode Line
Master CCLK
Goes Active
F
Pull INIT Low
and Stop
DS060_30_080400
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration Memory
Once More
LDC
Output
=
L,
HDC
Output
=
H
Boundary Scan
Instructions
Available:
I/O
Active
Keep Clearing
Configuration
Memory
Test MODE, Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
No
Yes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS05XL-4VQG100I | 制造商:Xilinx 功能描述:XCS05XL-4VQ100I |
| XCS05XL-5BG100C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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