收藏本站
参数资料
型号： XCS20XL-3BG208C
厂商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴达和Spartan - xL的家庭现场可编程门阵列
文件页数： 57/82页
文件大小： 863K
代理商： XCS20XL-3BG208C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
60
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
Spartan-XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Symbol
Device
Speed Grade
Units
-5
-4
Description
Min
Max
Min
Max
Setup Times
TECIK
Clock Enable (EC) to Clock (IK)
All devices
0.0
-
0.0
-
ns
TPICK
Pad to Clock (IK), no delay
All devices
1.0
-
1.2
-
ns
TPOCK
Pad to Fast Capture Latch Enable (OK), no delay
All devices
0.7
-
0.8
-
ns
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
TPID
Pad to I1, I2
All devices
-
0.9
-
1.1
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.1
-
2.5
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
1.0
-
1.1
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
1.1
-
1.2
ns
Delay Adder for Input with Full Delay Option
TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05XL
4.0
-
4.7
-
ns
XCS10XL
4.8
-
5.6
-
ns
XCS20XL
5.0
-
5.9
-
ns
XCS30XL
5.5
-
6.5
-
ns
XCS40XL
6.5
-
7.6
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
10.5
-
11.5
-
ns
TRRI
Delay from GSR input to any Q
XCS05XL
-
9.0
-
10.5
ns
XCS10XL
-
9.5
-
11.0
ns
XCS20XL
-
10.0
-
11.5
ns
XCS30XL
-
11.0
-
12.5
ns
XCS40XL
-
12.0
-
13.5
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
相关PDF资料
PDF描述
XCS20XL-3BG208I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG240C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG256C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG256I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG280C Spartan and Spartan-XL Families Field Programmable Gate Arrays
相关代理商/技术参数
参数描述
XCS20XL-3BG208I 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG240C 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG240I 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG256C 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG256I 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL FPGA
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*