- 您现在的位置：买卖IC网 > PDF目录300154 > XCS30-3TQ84I (Xilinx, Inc.) Spartan and Spartan-XL Families Field Programmable Gate Arrays PDF资料下载
参数资料
| 型号： | XCS30-3TQ84I |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴达和Spartan - xL的家庭现场可编程门阵列 |
| 文件页数： | 30/82页 |
| 文件大小： | 863K |
| 代理商： | XCS30-3TQ84I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
Spartan and Spartan-XL Families Field Programmable Gate Arrays
36
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
For more details on Configuration, refer to the Xilinx Appli-
cation Note "FPGA Configuration Guidelines" (XAPP090).
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user system. Start-up must make sure that the
user logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the configuration sig-
nals, and that the internal flip-flops are released from the
Global Set/Reset (GSR) at the right time.
Start-Up Initiation
Two conditions have to be met in order for the start-up
sequence to begin:
The chip's internal memory must be full, and
The configuration length count must be met, exactly.
In all configuration modes except Express mode, Spar-
tan/XL devices read the expected length count from the bit-
stream and store it in an internal register. The length count
varies according to the number of devices and the composi-
tion of the daisy chain. Each device also counts the number
of CCLKs during configuration.
In Express mode, there is no length count. The start-up
sequence for each device begins when the device has
received its quota of configuration data. Wiring the DONE
pins of several devices together delays start-up of all
devices until all are fully configured.
Start-Up Events
The device can be programmed to control three start-up
events.
The release of the open-drain DONE output
The termination of the Global Three-State and the
change of configuration-related pins to the user
function, activating all IOBs.
The termination of the Global Set/Reset initialization of
all CLB and IOB storage elements.
Figure 31 describes start-up timing in detail. The three
events — DONE going High, the internal GSR being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. This relative timing is selected by
options in the bitstream generation software. Heavy lines in
Figure 31 show the default timing. The thin lines indicate all
other possible timing options. The start-up logic must be
clocked until the "F" (Finished) state is reached.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. GSR is then released another clock period
later to make sure that user operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 31, but the designer can
modify it to meet particular requirements.
Start-Up Clock
Normally, the start-up sequence is controlled by the internal
device oscillator (CCLK), which is asynchronous to the sys-
tem clock. As a configuration option, they can be triggered
by an on-chip user net called UCLK. This user net can be
accessed by placing the STARTUP library symbol, and the
start-up
modes
are
known
as
UCLK_NOSYNC
or
UCLK_SYNC. This allows the device to wake up in synchro-
nism with the user system.
DONE Pin
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then be
used as input to the start-up control logic. This is called
“Start-up Timing Synchronous to Done In” and is selected
by either CCLK_SYNC or UCLK_SYNC. When DONE is not
used as an input, the operation is called “Start-up Timing
Not Synchronous to DONE In,” and is selected by either
CCLK_NOSYNC or UCLK_NOSYNC. Express mode con-
figuration always uses either CCLK_SYNC or UCLK_SYNC
timing, while the other configuration modes can use any of
the four timing sequences.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
相关PDF资料 |
PDF描述 |
|---|---|
| XCS30-3VQ144C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ208C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ208I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ240C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS30-3VQ100C | 功能描述:IC FPGA 5V C-TEMP 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XCS30-3VQ100I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ144C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3VQ208C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。