参数资料
型号: XPC850CVR50BUR2
厂商: Freescale Semiconductor
文件页数: 59/72页
文件大小: 0K
描述: IC MPU POWERQUICC 50MHZ 256-PBGA
标准包装: 500
系列: MPC8xx
处理器类型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
电压: 3.3V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-PBGA(23x23)
包装: 带卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
62
Freescale Semiconductor
CPM Electrical Characteristics
Table 25 provides the I2C (SCL > 100 KHz) timings.
Figure 61 shows the I2C bus timing.
Figure 61. I2C Bus Timing Diagram
210
SDL/SCL fall time
300.00
ns
211
Stop condition setup time
4.70
s
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 25. I2C Timing (SCL > 100 KHZ)
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master) 1
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2 * fSCL)
s
203
Low period of SCL
1/(2.2 * fSCL)
s
204
High period of SCL
1/(2.2 * fSCL)
s
205
Start condition setup time
1/(2.2 * fSCL)
s
206
Start condition hold time
1/(2.2 * fSCL)
s
207
Data hold time
0
s
208
Data setup time
1/(40 * fSCL)
s
209
SDL/SCL rise time
1/(10 * fSCL)
s
210
SDL/SCL fall time
1/(33 * fSCL)
s
211
Stop condition setup time
1/2(2.2 * fSCL)
s
Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED)
Num
Characteristic
All Frequencies
Unit
Min
Max
SCL
202
205
203
207
204
208
206
209
211
210
SDA
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